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s1d13503 graphics lcd controller s1d13503 technical manual issue date: 01/01/30 document number: x18a-q-001-07 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page iii vancouver design center issue date: 01/01/30 s1d13503 customer support information comprehensive support tools seiko epson corp. provides to the system designer and computer oem manufacturer a complete set of resources and tools for the development of graphics systems. evaluation / demonstration board ? assembled and fully tested graphics evaluation board with installation guide and schematics to borrow an evaluation board, please contact your local seiko epson corp. sales representative vga chip documentation technical manual includes data sheet, application notes, and programmer?s reference software video bios oem utilities user utilities evaluation software to obtain these programs, contact application engineering support application engineering support engineering and sales support is provided by: japan seiko epson corporation electronic devices marketing division 421-8, hino, hino-shi tokyo 191-8501, japan tel: 042-587-5812 fax: 042-587-5564 http://www.epson.co.jp hong kong epson hong kong ltd. 20/f., harbour centre 25 harbour road wanchai, hong kong tel: 2585-4600 fax: 2827-4346 taiwan, r.o.c. epson taiwan technology & trading ltd. 10f, no. 287 nanking east road sec. 3, taipei, taiwan, r.o.c. tel: 02-2717-7360 fax: 02-2712-9164 singapore epson singapore pte., ltd. no. 1 temasek avenue #36-00 millenia tower singapore, 039192 tel: 337-7911 fax: 334-2716 europe epson europe electronics gmbh riesstrasse 15 80992 munich, germany tel: 089-14005-0 fax: 089-14005-110 north america epson electronics america, inc. 150 river oaks parkway san jose, ca 95134, usa tel: (408) 922-0200 fax: (408) 922-0238 http://www.eea.epson.com
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epson research and development page v vancouver design center issue date: 01/01/30 s1d13503 table of contents introduction s1d13503 graphics lcd controller data sheet specification s1d13503 hardware functional specification programmer?s reference s1d13503 programming notes and examples utilities 13503show.exe display utility 13503virt.exe display utility 13503bios.com display utility 13503mode.exe display utility 13503pd.exe power down utility 13503read.exe diagnostic utility evaluation s5u13503b00c rev 1 evaluation board user manual application notes power consumption isa bus interface considerations mc68340 interface considerations lcd panel options/memory requirements s1d13503/s1d13502 feature comparison
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graphics s1d13503 x18a-c-002-03 1 january 2001 s1d13503 graphics lcd controller description the s1d13503 is a dot matrix graphic lcd controller supporting resolutions up to 1024x1024. it is capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades. design flexibility allows the s1d13503 to interface to either an mc68000 family microprocessor or an 8/16-bit mpu/bus with minimum external logic. the static ram (sram) interface used for the display buffer is optimized for speed and performance, supporting up to 128k bytes. two power save modes, combined with operating voltages of 2.7 volts through 5.5 volts, allow for a wide range of applications while providing minimum power consumption. features cpu interface pin compatible with the s1d13502. 16-bit 16 mhz mc68xxx mpu interface. 8/16-bit mpu interface controlled by a ready (or wait#) signal. option to use built-in index register or direct-map- ping to access one of sixteen internal registers. memory interface 8/16-bit sram interface configurations: 128k bytes using one 64kx16 srams. 128k bytes using two 64kx8 srams. 64k bytes using two 32kx8 srams. 40k bytes using one 8kx8 and one 32kx8 sram. 32k bytes using one 32kx8 sram. 16k bytes using two 8kx8 srams. 8k bytes using one 8kx8 sram. display modes black-and-white display. 2/4 bits-per-pixel, 4/16-level gray-scale display. 2/4/8 bits-per-pixel, 4/16/256-level color display. display support single-panel, single-drive passive display. dual-panel, dual-drive passive display. maximum number of vertical lines: 1,024 lines (single-panel, single-drive display). 2,048 lines (dual-panel, dual-drive display). split screen display support allowing two different images to be simultaneously displayed. virtual display support (displays images larger than the panel size through the use of panning). clock source 2-terminal crystal or external oscillator. power down modes low power consumption. two software power-save modes. package qfp5-100-s2 package (f00a). qfp15-100-std package (f01a).
graphics s1d13503 x18a-c-002-03 2 system block diagram qfp5-100-s2 s1d13503 flat panel digital out cpu sram control clock clock (s1d13503f00a) qfp15-100-std (s1d13503f01a) contact your sales representative for these comprehensive design tools: ? s1d13503 technical manual s5u13503 evaluation boards cpu independent software utilities japan seiko epson corporation electronic devices marketing division 421-8, hino, hino-shi tokyo 191-8501, japan tel: 042-587-5812 fax: 042-587-5564 http://www.epson.co.jp hong kong epson hong kong ltd. 20/f., harbour centre 25 harbour road wanchai, hong kong tel: 2585-4600 fax: 2827-4346 taiwan epson taiwan technology & trading ltd. 10f, no. 287 nanking east road sec. 3, taipei, taiwan tel: 02-2717-7360 fax: 02-2712-9164 singapore epson singapore pte., ltd. no. 1 temasek avenue #36-00 millenia tower singapore, 039192 tel: 337-7911 fax: 334-2716 europe epson europe electronics gmbh riesstrasse 15 80992 munich, germany tel: 089-14005-0 fax: 089-14005-110 north america epson electronics america, inc. 150 river oaks parkway san jose, ca 95134, usa tel: (408) 922-0200 fax: (408) 922-0238 http://www.eea.epson.com copyright ?1997, 2001 epson research and development, inc. all rights reserved. vdc information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/ epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the con tents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or inte rnational patent laws. epson is a registered trademark of seiko epson corporation. microsoft and windows are registered trademarks of microsoft corpo ration.
s1d13503 dot matrix graphics color lcd controller hardware functional specification document number: x18a-a-001-08 copyright ? 1997, 2001epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 overview description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 display support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 typical system block diagrams . . . . . . . . . . . . . . . . . . . . . . 12 3.1 16-bit mc68000 mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 mpu with ready (or wait#) signal . . . . . . . . . . . . . . . . . . . . . . 13 3.3 isa bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 functional block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.1 bus signal translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.3 sequence controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.4 lcd panel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.5 look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.6 port decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.7 memory decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.8 data bus conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.9 address generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.10 mpu / crt selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.11 display data formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.12 clock inputs / timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5.13 sram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 summary of configuration options . . . . . . . . . . . . . . . . . . . . . . . . 26 6 d.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 a.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.1 mc68000 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.2 non-mc68000, mpu/bus with ready (or wait#) signal . . . . . . . . . . . . . . . 33 7.2 clock input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.1 recommended clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
page 4 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.3 display memory interface timing . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.1 write data to display memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3.2 read data from display memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 7.4 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4.1 lcd interface timing - 4-bit single, 8-bit single/dual monochrome panels . . . . . . . 41 7.4.2 lcd interface timing - 4-bit single color panel . . . . . . . . . . . . . . . . . . . . . . 44 7.4.3 lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels . . . 46 7.4.4 lcd interface timing - 16-bit single/dual color panels . . . . . . . . . . . . . . . . . . 48 7.4.5 lcd interface timing - 8-bit single color panels format 1 . . . . . . . . . . . . . . . . 50 7.4.6 lcd interface options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8 hardware register interface . . . . . . . . . . . . . . . . . . . . . . . .61 8.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.2 look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.1 gray shade display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.2 color display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.3 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.1 power save mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.2 power save mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.3.3 power save mode function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.4 pin states in power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9 display memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . .79 9.1 sram configurations supported . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.1 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.1.2 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.2 sram access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2.1 8-bit display memory interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2.2 16-bit display memory interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.3 frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.1 for single panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.2 for dual panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.4 memory size calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.5 memory size requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
epson research and development page 5 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 list of tables table 4-1: pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5-1: bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5-2: display memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 5-3: lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5-4: clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5-5: power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5-6: summary of power on / reset options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 5-7: i/o and memory addressing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 6-1: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 6-2: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 6-3: input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 6-4: output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7-1: iow# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7-2: ior# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 7-3: memw# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 7-4: memr# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7-5: iow# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 7-6: ior# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 7-7: memw# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 7-8: memr# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 7-9: clock input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 7-10: write data to display memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 7-11: read data from display memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 7-12: lcd interface timing - 4-bit single and 8-bit single/dual monochrome panel . . . . . . . . . . . 42 table 7-13: lcd interface timing - 4-bit single color panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7-14: lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels . . . . . . . . . 47 table 7-15: lcd interface timing - 16-bit single/dual color panels . . . . . . . . . . . . . . . . . . . . . . . 49 table 7-16: lcd interface timing - 8-bit single color panels format 1 . . . . . . . . . . . . . . . . . . . . . . 51 table 8-1: gray shade/color mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 8-2: lcd data width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8-3: maximum value of line byte count register - 8-bit display memory interface . . . . . . . . . . . 64 table 8-4: maximum value of line byte count register - 16-bit display memory interface . . . . . . . . . . 64 table 8-5: power save mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 8-6: id bit usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 8-7: look-up table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 8-8: look-up table configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 8-9: power save mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 8-10: power save mode function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 8-11: pin states in power save modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 9-1: 8-bit display memory interface sram access time . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 9-2: 16-bit display memory interface sram access time. . . . . . . . . . . . . . . . . . . . . . . . . 83 table 9-3: memory size requirement: number of horizontal pixels = 640 . . . . . . . . . . . . . . . . . . . .85 table 9-4: memory size requirement: number of horizontal pixels = 480 . . . . . . . . . . . . . . . . . . . .86 table 9-5: memory size requirement: number of horizontal pixels = 320 . . . . . . . . . . . . . . . . . . . .86
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epson research and development page 7 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 list of figures figure 1: 16-bit 68000 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 2: 8-bit mode, example: z80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 3: 16-bit mode, example: i8086 (maximum mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4: 8-bit mode (isa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5: 16-bit mode (isa). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: s1d13503 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8: s1d13503 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9: s1d13503 pad diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10: iow# timing (mc68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 11: ior# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 12: memw# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 13: memr# timing (mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 14: iow# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 15: ior# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 16: memw# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 17: memr# timing (non-mc68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 18: clock input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 19: recommended clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 20: write data to display memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 21: read data from display memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 22: lcd interface timing - monochrome panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 23: lcd interface timing - 4-bit single color panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24: lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels . . . . . . . . . 46 figure 25: lcd interface timing - 16-bit single/dual color panels . . . . . . . . . . . . . . . . . . . . . . . 48 figure 26: lcd interface timing - 8-bit single color panels format 1 . . . . . . . . . . . . . . . . . . . . . . 50 figure 27: 4-bit single monochrome panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 28: 8-bit single monochrome panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 29: 8-bit dual monochrome panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 30: 4-bit single color panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 31: 8-bit single color panel timing - format 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 32: 8-bit single color panel timing - format 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 33: 8-bit dual color panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 34: external circuit required for 16-bit panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 35: 16-bit single color panel timing with external circuit . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 36: 16-bit dual color panel timing with external circuit . . . . . . . . . . . . . . . . . . . . . . . . . 60
page 8 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 37: 4-level gray-shade mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . 72 figure 38: 16-level gray-shade mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . 73 figure 39: 4-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 40: 16-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 41: 256-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 42: 8-bit mode - 8k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 43: 8-bit mode - 16k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 44: 8-bit mode - 32k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 45: 8-bit mode - 40k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 46: 8-bit mode - 64k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 47: 16-bit mode - 16k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 48: 16-bit mode - 64k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 49: 16-bit mode - 128k bytes sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 50: mechanical drawing qfp5-100-s2 (s1d13503) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 51: mechanical drawing qfp15-100-std (s1d13503). . . . . . . . . . . . . . . . . . . . . . . . . . 88
epson research and development page 9 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 1 introduction 1.1 scope this is the functional specification for the s1d13503 dot matrix graphic color lcd controller. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences, video subsystem designers and software developers. 1.2 overview description this device is designed for products where low cost, low power consumption, and low component count are the major design considerations. this chip operates from 2.7 volts to 5.5 volts and up to 25mhz to suit different power consumption, speed and cost requirements. the s1d13503 offers a flexible microprocessor interface, and is pin compatible with the s1d13502 within the same package types (e.g. the 13503d0a is pin compatible with the 13502; the 13503 is pin compatible with the 13502). the s1d13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. in gray shade modes, a 16x4 look-up table is provided to allow remapping of the 16 possible gray shades displayed on the lcd panel. in color modes, three 16x4 look-up tables are provided to allow remapping of the 4096 possible colors displayed on the lcd panel. the s1d13503s1d13503 can interface to an mc68000 family microprocessor or an 8/16-bit mpu/bus with minimum external ?glue? logic. this device can directly control up to 128k bytes of static ram with a 16-bit data path, or up to 64k bytes with an 8-bit data path.
page 10 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 2 features 2.1 technology low power cmos 2.7 to 5.5 volt operation 100 pin qfp5-s2 surface mount package 100 pin qfp15-std surface mount package 2.2 system maximum 25 mhz input clock (or pixel clock) 2-terminal crystal input for internal oscillator or direct connection to external clock source maximum 16 mhz, 16-bit mc68000 mpu interface 8-bit or 16-bit mpu/bus interface with memory accesses controlled by a ready (or wait#) signal option to use built-in index register or direct-mapping to access one of sixteen internal registers 8-bit or 16-bit sram data bus interface configurations display memory configurations : 128k bytes using one 64kx16 sram 128k bytes using two 64kx8 srams 64k bytes using two 32kx8 srams 40k bytes using one 8kx8 and one 32kx8 sram 32k bytes using one 32kx8 sram 16k bytes using two 8kx8 srams 8k bytes using one 8kx8 sram 2.3 display modes 1 bit-per-pixel, black-and-white display mode 2/4 bits-per-pixel, 4/16 level gray shade display modes 2/4/8 bits-per-pixel, 4/16/256 level color display modes one 16x4 look-up table provided for gray shade display modes three 16x4 look-up tables provided for color display modes maximum 16 shades of gray maximum 256 simultaneous colors from a possible 4096 colors split screen display mode (see aux[0a]) virtual display mode (see aux[0d]) note 256 color display mode support requires a 16-bit display memory interface
epson research and development page 11 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 2.4 display support example resolutions: 1024 x 768 black-and-white 640 x 480 with 4 colors/grays 640 x 400 with 16 colors/grays 320 x 240 with 256 colors passive monochrome lcd panels: 4-bit single (4-bit data transfer) 8-bit single (8-bit data transfer) 8-bit dual (4-bit data transfer for each half panel) passive color lcd panels: 4-bit single (4-bit data transfer) 8-bit single (8-bit data transfer) 8-bit dual (4-bit data transfer for each half panel) 16-bit single (8-bit data transfer with external circuit) 16-bit dual (8-bit data transfer with external circuit) see section 9.5 on page 85 for complete details 2.5 power management two software power-save modes low power consumption panel power control switch (see aux[01] bit 4)
page 12 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 3 typical system block diagrams the following figures show typical system implementations of the s1d13503. all of the following block diagrams are shown without sram or lcd display. refer to the interface specific application notes for complete details. 3.1 16-bit mc68000 mpu figure 1: 16-bit 68000 series (example implementation only - actual may vary) s1d13503 memcs# iocs# mc68000 dtack# d0 to d15 a1 to a19 ab1 to ab19 db0 to db15 iow# ior# decoder as# r/w# bhe# uds# ready a20 to a23 ab0 lds# decoder a14 to a16 a10 to a19 fc0 to fc1
epson research and development page 13 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 3.2 mpu with ready (or wait#) signal figure 2: 8-bit mode, example: z80 (example implementation only - actual may vary) figure 3: 16-bit mode, example: i8086 (maximum mode) (example implementation only - actual may vary) memcs# memw# memr# ready db0 to db7 ab0 to ab15 iocs# iow# ior# reset s1d13503 z80 reset# d0 to d7 wa i t # a0 to a15 wr# rd# decoder iorq# a10 to a15 decoder mreq# mi# 8086 (maximum mode) clk ready reset# rdy memw# memr# ready db0 to db15 ab0 to ab15 iow# ior# reset s1d13503 8284a d0 to d15 t oe clk s2# s1# s0# den mrdc# amwc# iorc# aiowc# dt/r clk ready reset# 8288 ab16 to ab19 m/io# bhe# a0 to a16 stb decoder a16 to a19 s2# s1# s0# ale bhe# ad0 to ad15 a16 bhe# memcs# iocs# transceiver
page 14 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 3.3 isa bus figure 4: 8-bit mode (isa) (example implementation only - actual may vary) figure 5: 16-bit mode (isa) (example implementation only - actual may vary) s1d13503 memcs# memw# memr# ready 8-bit isa bus smemw# smemr# iochrdy refresh sa0 to sa19 sd0 to sd7 db0 to db7 ab0 to ab19 decoder sa16 to sa13 iocs# iow# ior# reset reset# sa10 to sa15 aen iow# ior# decoder 0ws# optional decoder sa(1 or 4) through sa9 s1d13503 memcs# memw# memr# ready 16-bit isa bus smemw# smemr# iochrdy refresh sa0 to sa19 sd0 to sd15 db0 to db15 ab0 to ab19 decoder iocs# iow# ior# reset reset# decoder sa10 to sa15 aen iow# ior# iocs16# sa(1 or 4) through sa9 bhe# sbhe# decoder memcs16# la17 to la23 sa16 to sa14 decoder
epson research and development page 15 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 3.4 internal block diagram figure 6: internal block diagram 3.5 functional block descriptions 3.5.1 bus signal translation according to configuration setting vd2, bus signal translation translates mc68000 type mpu signals, or ready type mpu signals to internal bus interface signals. 3.5.2 control registers the control register contains 16 internal control and configuration registers. these registers can be accessed by either direct-mapping or by using the built-in internal index register. 3.5.3 sequence controller the sequence controller generates horizontal and vertical display timings according to the configuration registers settings. 3.5.4 lcd panel interface the lcd panel interface performs frame rate modulation and output data pattern formatting for both passive monochrome and passive color lcd panels. bus control registers signal translation port memory data bus timing generator sequence address mpu/crt sram interface lookup lcd decoder decoder conversion oscillator power save selector display data formatter generator table controller panel interface lcdenb ud[3:0] ld[3:0] lp, yd, xscl, osc1 osc2 vwe# voe# va[15:0] vcs0#, vcs1# vd[15:0] ior#, iow#, iocs#, memcs#, memr#, memw#, bhe#, ab[19:0] ready db[15:0] wf(xscl2)
page 16 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 3.5.5 look-up table the look-up table contains three 16x4-bit wide palettes. in gray shade modes, the ?green? palette can be configured for the re-mapping of 16 possible shades of gray. in color modes, all three palettes can be configured for the re-mapping of 4096 possible colors. 3.5.6 port decoder according to configuration settings vd1, vd12 - vd4, iocs# and address lines ab9-1, the port decoder validates a given i/o cycle. 3.5.7 memory decoder according to configuration settings vd15 - vd13, memcs# and address lines ab19-17, the memory decoder validates a given memory cycle. 3.5.8 data bus conversion according to configuration setting vd0, data bus conversion maps the external data bus, either 8-bit or 16-bit, into the internal odd and even data bus. 3.5.9 address generator the address generator generates display refresh addresses to be used to access display memory. 3.5.10 mpu / crt selector the mpu / crt selector grants access to the display memory from either the mpu or the display refresh circuitry. 3.5.11 display data formatter the display data formatter reads in the display data from the display memory and outputs the correct format for all supported gray shade and color selections. 3.5.12 clock inputs / timing clock inputs / timing generates the internal master clock according to gray-level / color selected and display memory interface. the master clock (mclk) can be: - mclk = input clock - mclk = 1/2 input clock - mclk = 1/4 input clock. pixel clock = input clock = f osc. 3.5.13 sram interface the sram interface generates the necessary signals to interface to the display memory (sram).
epson research and development page 17 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 4 pinout diagram figure 7: s1d13503f00a pinout diagram package type: 100 pin surface mount qfp5-s2. note * pin 80 = wf in all display modes except format 1 for 8-bit single color panel. * pin 80 = xscl2 in format 1 for 8-bit single color panel. 1 2 3 4 5 6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 81 82 83 84 85 32 33 34 35 36 37 38 39 40 41 42 43 44 45 50 49 48 47 46 31 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 db6 db5 db4 db3 db2 db1 db0 osc2 osc1 bhe# ready memr# memw# memcs# ior# iow# iocs# voe# lcdenb xscl ab19 va 0 va 1 va 2 va 3 va 4 va 5 va 6 va 7 va 8 va 9 va 1 0 vd0 vd1 vd2 vd3 vd4 vd5 vd6 s1d13503f00a db7 v ss v dd db8 db9 db10 db11 db12 db13 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 db14 wf/xscl2* lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va 1 5 va 1 4 va 1 3 va 1 2 va 11 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss vd7 reset
page 18 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 8: s1d13503f01a pinout diagram package type: 100 pin surface mount qfp15-std. note * pin 77 = wf in all display modes except format 1 for 8-bit single color panel. * pin 77 = xscl2 in format 1 for 8-bit single color panel. 1 2 3 4 5 6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 81 82 83 84 85 32 33 34 35 36 37 38 39 40 41 42 43 44 45 50 49 48 47 46 31 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 db6 db5 db4 db3 db2 db1 db0 osc2 osc1 bhe# ready memr# memw# memcs# ior# iow# iocs# voe# lcdenb xscl ab19 va 0 va 1 va 2 va 3 va 4 va 5 va 6 va 7 va 8 va 9 va 1 0 vd0 vd1 vd2 vd3 vd4 vd5 vd6 s1d13503f01a db7 v dd vss db8 db9 db10 db11 db12 db13 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 ab14 ab15 ab16 ab17 ab18 db14 wf/xscl2* lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va 1 5 va 1 4 va 1 3 va 1 2 va 1 1 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v ss vd7 reset v dd
epson research and development page 19 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 9: s1d13503d00a pad diagram note * pad 97 = wf in all display modes except format 1 for 8-bit single color panel. * pad 97 = xscl2 in format 1 for 8-bit single color panel. db7 v ss v dd db8 db9 db10 db11 db12 db13 db15 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 db14 ab14 ab15 ab16 ab17 ab18 ab19 va 0 va 1 va 2 va 3 va 4 va 5 va 6 va 7 va 8 va 9 va 1 0 vd0 vd1 vd2 vd3 vd4 vd5 vd6 reset wf/xscl2* lp yd ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 vcs1# vcs0# vwe# va 1 5 va 1 4 va 1 3 va 1 2 va 1 1 vd15 vd14 vd13 vd12 vd11 vd10 vd9 vd8 v dd v ss vd7 db6 db5 db4 db3 db2 db1 db0 osc2 osc1 bhe# ready memr# memw# memcs# ior# iow# iocs# voe# lcdenb xscl 110 20 30 40 50 60 70 80 90 100 dummy pad dummy pad chip size chip thickness pad size pad pitch 5.030 mm x 5.030 mm 0.400 mm 0.090 mm x 0.090 mm 0.126 mm (min.) = = = = s1d13503d00a 110 120
page 20 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 table 4-1: pad coordinates pad no. pin name pad center coordinate pad no. pin name pad center coordinate xy xy 1 vss -2.165 -2.390 37 reset 2.390 -1.535 2 --- -2.000 -2.390 38 va0 2.390 -1.388 3 vdd -1.840 -2.390 39 va1 2.390 -1.246 4 db8 -1.685 -2.390 40 va2 2.390 -1.106 5 db9 -1.535 -2.390 41 --- 2.390 -0.969 6 db10 -1.388 -2.390 42 va3 2.390 -0.835 7 db11 -1.246 -2.390 43 va4 2.390 -0.703 8 db12 -1.106 -2.390 44 --- 2.390 -0.573 9 db13 -0.969 -2.390 45 va5 2.390 -0.444 10 db14 -0.835 -2.390 46 va6 2.390 -0.317 11 db15 -0.703 -2.390 47 --- 2.390 -0.190 12 --- -0.573 -2.390 48 va7 2.390 -0.063 13 ab0 -0.444 -2.390 49 va8 2.390 0.063 14 ab1 -0.317 -2.390 50 --- 2.390 0.190 15 ab2 -0.190 -2.390 51 va9 2.390 0.317 16 ab3 -0.063 -2.390 52 va10 2.390 0.444 17 ab4 0.063 -2.390 53 --- 2.390 0.573 18 ab5 0.190 -2.390 54 vd0 2.390 0.703 19 ab6 0.317 -2.390 55 vd1 2.390 0.835 20 ab7 0.444 -2.390 56 --- 2.390 0.969 21 --- 0.573 -2.390 57 vd2 2.390 1.106 22 ab8 0.703 -2.390 58 vd3 2.390 1.246 23 ab9 0.835 -2.390 59 vd4 2.390 1.388 24 ab10 0.969 -2.390 60 vd5 2.390 1.535 25 ab11 1.106 -2.390 61 vd6 2.390 1.685 26 ab12 1.246 -2.390 62 --- 2.390 1.840 27 ab13 1.388 -2.390 63 --- 2.390 2.000 28 ab14 1.535 -2.390 64 vd7 2.390 2.165 29 ab15 1.685 -2.390 65 vss 2.165 2.390 30 ab16 1.840 -2.390 66 --- 2.000 2.390 31 --- 2.000 -2.390 67 vdd 1.840 2.390 32 ab17 2.165 -2.390 68 vd8 1.685 2.390 33 ab18 2.390 -2.340 69 vd9 1.535 2.390 34 --- 2.390 -2.000 70 vd10 1.388 2.390 35 --- 2.390 -1.840 71 vd11 1.246 2.390 36 ab19 2.390 -1.685 72 vd12 1.106 2.390
epson research and development page 21 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 73 vd13 0.969 2.390 102 voe# -2.390 1.388 74 vd14 0.835 2.390 103 iocs# -2.390 1.246 75 vd15 0.703 2.390 104 iow# -2.390 1.106 76 --- 0.573 2.390 105 --- -2.390 0.969 77 va11 0.444 2.390 106 ior# -2.390 0.835 78 va12 0.317 2.390 107 memcs# -2.390 0.703 79 va13 0.190 2.390 108 --- -2.390 0.573 80 va14 0.063 2.390 109 memw# -2.390 0.444 81 va15 -0.063 2.390 110 memr# -2.390 0.317 82 vwe# -0.190 2.390 111 --- -2.390 0.190 83 vcs0# -0.317 2.390 112 ready -2.390 0.063 84 vcs1# -0.444 2.390 113 bhe# -2.390 -0.063 85 --- -0.573 2.390 114 --- -2.390 -0.190 86 ud3 -0.703 2.390 115 osc1 -2.390 -0.317 87 ud2 -0.835 2.390 116 osc2 -2.390 -0.444 88 ud1 -0.969 2.390 117 --- -2.390 -0.573 89 ud0 -1.106 2.390 118 db0 -2.390 -0.703 90 ld3 -1.246 2.390 119 db1 -2.390 -0.835 91 ld2 -1.388 2.390 120 --- -2.390 -0.969 92 ld1 -1.535 2.390 121 db2 -2.390 -1.106 93 ld0 -1.685 2.390 122 db3 -2.390 -1.246 94 yd -1.840 2.390 123 db4 -2.390 -1.388 95 --- -2.000 2.390 124 db5 -2.390 -1.535 96 lp -2.340 2.390 125 db6 -2.390 -1.685 97 wf/xscl2 -2.390 2.165 126 --- -2.390 -1.840 98 --- -2.390 2.000 127 --- -2.390 -2.000 99 --- -2.390 1.840 128 db7 -2.390 -2.165 100 xscl -2.390 1.685 129 dummy pad 2.390 2.390 101 lcdenb -2.390 1.535 130 dummy pad -2.390 -2.390 table 4-1: pad coordinates pad no. pin name pad center coordinate pad no. pin name pad center coordinate xy xy
page 22 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 5 pin description 5.1 description key: i=input o=output i/o = bidirectional (input/output) p=power pin cox = cmos level output driver, x denotes driver type (see table 6-4, ?output specifications,? on page 28) coxs = cmos level output driver with slew rate control for noise reduction, x denotes driver type (see table 6-4, ?output specifications,? on page 28) tsx = tri-state cmos level output driver, x denotes driver type (see table 6-4, ?output specifications,? on page 28) tsxd2 = tri-state cmos level output driver with pull down resistor (typical values of 100k ?/200? at 5v/3.0v respectively), x denotes driver type (see table 6-4, ?output specifications,? on page 28) ttl = ttl level input (v dd = 5.0v, see table 6-3, ?input specifications,? on page 27) ttls = ttl level input with hysteresis table 5-1: bus interface pin name type f00a pin # f01a pin # d00a pad # driver description db0- db15 i/o 94 - 100, 1, 4 -11 91 - 98, 1 - 8 118- 119, 121- 125, 128, 4-11 ts2 these pins are connected to the system data bus. in 8-bit bus mode, db8-db15 must be tied to v dd . ab0 i 12 9 13 ttls in mc68000 mpu interface, this pin is connected to the upper data strobe (uds#) pin of mc68000. in other mpu/bus interfaces, this pin is connected to the system address bus. ab1- ab19 i 13 - 31 10 - 28 14-20, 22-30, 32-33, 36 ttl these pins are connected to the system address bus. bhe# i 91 88 113 ttls in mc68000 mpu interface, this pin is connected to the lower data strobe (lds#) pin of mc68000. in other mpu/bus interfaces, this pin is the byte high enable input for use with 16-bit system. in 8-bit bus mode tie the bhe# input to v dd . iocs# i 84 81 103 ttls active low input to select one of sixteen internal registers.
epson research and development page 23 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 iow# i 85 82 104 ttls in mc68000 mpu interface, this pin is connected to the r/w# pin of mc68000. this input pin defines whether the data transfer is a read (active high) or write (active low) cycle. in other mpu/bus interfaces, this is the active low input to write data into an internal register. ior# i 86 83 106 ttls in mc68000 mpu interface, this pin is connected to the as# pin of mc68000. this input pin indicates a valid address is available on the address bus. in other mpu/bus interfaces, this is the active low input to read data from an internal register. memcs# i 87 84 107 ttls active low input to indicate a memory cycle. memw# i 88 85 109 ttls active low input to indicate a memory write cycle. this pin should be tied to v dd in an mc68000 mpu interface. memr# i 89 86 110 ttls active low input to indicate a memory read cycle. this pin should be tied to v dd in an mc68000 mpu interface. readyo 9087112ts3 for mc68000 mpu interface, this pin is connected to the dtack# pin of mc68000 and is driven low when the data transfer is complete. in other mpu/bus interfaces, this output is driven low to force the system to insert wait states when needed. ready is placed in a high impedance (hi-z) state after the transfer is completed. reset i 32 29 37 ttls active high input to force all signals to their inactive states. table 5-1: bus interface pin name type f00a pin # f01a pin # d00a pad # driver description
page 24 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 table 5-2: display memory interface pin name type f00a pin # f01a pin # d00a pad # driver description vd0- vd15 i/o 44 - 51, 54 - 61 41 - 48, 51 - 58 54-55, 57-61, 64, 68-75 ts1d2 these pins are connected to the display memory data bus. for 16- bit interface, vd0-vd7 are connected to the display memory data bus of even byte addresses and vd8-vd15 are connected to the display memory data bus of odd byte addresses. the output drivers of these pins are placed in a high impedance state when reset is high. on the falling edge of reset, the values of vd0-vd15 are latched into the chip to configure various hardware options (see section table 5-6: on page 26). vd0-vd15 each have an internal pull-down resistor (see section table 6-3: on page 27). va0- va15 o 33 - 43, 62 - 66 30 - 40 59 - 63 38-40, 42-43, 45-46, 48-49, 51-52, 77-81 co1 these pins are connected to the display memory address bus. vcs1# o 69 66 84 co1 active low chip-select output to the second or odd byte address sram. see display memory interface section for details. vcs0# o 68 65 83 co1 active low chip-select output to the first or even byte address sram. see display memory interface section for details. vwe#o676482co1 active low output used for writing data to the display memory. this pin is connected to the we# input of the srams. voe#o8380102co1 active low output to enable reading of data from the display memory. this pin is connected to the oe# input of the srams.
epson research and development page 25 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table 5-3: lcd interface pin name fpdi-1 tm pin name a a vesa flat panel display interface standard (fpdi-1 tm ) type f00a pin # f01a pin # d00a pad # driver description ud3-ud0 ld3-ld0 ud3-ud0 ud3-ld0 o 70 - 73 74 - 77 67 - 70 71 - 74 86 - 89 90 - 93 co3s panel display data bus. the data format depends on the specific panel connected. for 4-bit single panels, ld3-ld0 are driven low (0 state). xscl fpshift o 81 78 100 co3 display data shift clock. data is shifted into the lcd x-drivers on the falling edge of this signal. lp fpline o 79 76 96 co3 display data latch clock. the falling edge of this signal is used to latch a row of display data in the lcd x-drivers and to turn on the y driver (row driver). wf/ xscl2 mod fpshift2 o80 77 97 co3 for format 1 of 8-bit single color panels this is the second shift clock. for all other modes, this is the lcd backplane bias signal. this output toggles once every frame, or as programmed in aux[05] bits 7-2. yd fpframe o 78 75 94 co3 vertical scanning start pulse. a logic ?1? on this signal, sampled by the lcd module on the falling edge of lp, is used by the panel y driver (row driver) to indicate the start of the vertical frame. lcdenb ----- o82 79 101 co2 lcd enable signal output. it can be used externally to turn off the panel supply voltage and backlight. table 5-4: clock inputs pin name type f00a pin # f01a pin # d00a pad # driver description osc1i9289115* this pin, along with osc2, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. if an external oscillator is used as a clock source, then this pin is the clock input. osc2o9390116* this pin, along with osc1, is the 2-terminal crystal interface when using a 2-terminal crystal as the clock input. if an external oscillator is used as a clock source this pin should be left unconnected. table 5-5: power supply pin name type f00a pin # f01a pin # d00a pad # driver description v dd p 3, 53 50, 100 3, 67 p voltage supply v ss p 2, 52 49, 99 1, 65 p voltage ground
page 26 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 5.2 summary of configuration options the s1d13503 requires some configuration information on power-up. this information is provided through the sram data lines vd[0...15]. the state of these pins are read on the falling edge of reset and used to configure the following options: note the s1d13503 has internal pulldown resistors on these pins and therefore will be pulled down and read on a logic ?0? after reset. if pullup resistors are required refer to table 6-3, ?input specifications,? on page 27 for pulldown resistor values. example: if an isa bus (no byte swap) with memory segment ?a? and i/o location 300h are used, the corresponding settings of vd15-vd0 would be: where x = don?t care; 1 = connected to pull-up resistor; 0 = no pull-up resistor table 5-6: summary of power on / reset options pin name value on this pin at falling edge of reset is used to configure: (1/0) 1 0 vd0 16-bit host bus interface 8-bit host bus interface vd1 use direct-mapping for i/o accesses use internal index register for i/o accesses vd2 mc68000 mpu interface mpu / bus interface with memory accesses controlled by a ready (wait#) signal vd3 swap of high and low data bytes in 16-bit bus interface no byte swap of high and low data bytes in 16-bit bus interface vd12-vd4 select i/o mapping address bits [9:1]. these nine bits are latched on power-up and are compared to the mpu address bits [9-1]. a valid i/o cycle combined with a valid address will enable the internal i/o decoder. therefore, both types of i/o mapping are limited to even address boundaries to determine either the absolute or indexed i/o address of the first register. note that a ?valid i/o cycle? includes iocs# being toggled low. vd15-vd13 select memory mapping address bits [3:1] these three bits are latched on power-up and are compared to the mpu address bits [19-17]. a valid memory cycle combined with a valid address will enable the internal memory decoder. as only the three most significant bits of the address are compared, the maximum amount of memory supported is 128k bytes. note that a ?valid memory cycle? includes memcs# being toggled low. when using 128k byte memory it must be mapped at an even address such that all 128k bytes is available without a change in state on a17, as this would invalidate the internal compare logic. table 5-7: i/o and memory addressing example 8-bit isa bus 16-bit isa bus pin name index register direct mapping index register direct mapping vd00011 vd10 101 vd20000 vd30000 vd12-vd4 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx vd15-vd13 101 101 101 101
epson research and development page 27 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 6 d.c. characteristics table 6-1: absolute maximum ratings symbol parameter rating units v dd supply voltage -0.3 to + 6.0 v v in input voltage -0.3 to v dd + 0.5 v v out output voltage -0.3 to v dd + 0.5 v t stg storage temperature -65 to 150 c t sol solder temperature/time 260 for 10 sec. max at lead c table 6-2: recommended operating conditions symbol parameter condition min typ max units v dd supply voltage v ss = 0 v 2.7 3.0/3.3/5.0 5.5 v v in input voltage v ss -- v dd v i opr operating current f osc = 6 mhz 256 colors 4.5/5.0/11 ma t opr operating temperature -40 25 85 c p typ typical active power consumption f osc = 6 mhz 256 colors 13.5/16.5/55 mw table 6-3: input specifications symbol parameter condition min typ max units v il low level input voltage v dd = 4.5v v dd = 3.0v v dd = 2.7v 0.8 0.4 0.3 v v ih high level input voltage v dd = 5.5v v dd = 3.6v v dd = 3.3v 2.0 1.3 1.2 v v t+ positive-going threshold v dd = 5.0 v dd = 3.3 v dd = 3.0 2.4 1.4 1.3 v v t- negative-going threshold v dd = 5.0 v dd = 3.3 v dd = 3.0 0.6 0.5 0.4 v v h hysteresis voltage v dd = 5.0 v dd = 3.3 v dd = 3.0 0.1 0.1 0.1 v i iz input leakage current -- -1 1 a
page 28 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 c in input pin capacitance f =1 mhz, v dd = 0v 12 pf r pd pull down resistance v dd = 5.0v v i = v dd 50 100 200 k ? r pd pull down resistance v dd = 3.3v v i = v dd 90 180 360 k ? r pd pull down resistance v dd = 3.0v v i = v dd 100 200 400 k ? table 6-4: output specifications symbol parameter condition min typ max units v ol (5.0v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i ol = 4 ma i ol = 8 ma i ol = 12 ma 0.4 v v ol (3.3v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i ol = 2 ma i ol = 4 ma i ol = 6 ma 0.3 v v ol (3.0v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i ol = 1.8 ma i ol = 3.5 ma i ol = 5 ma 0.3 v v oh (5.0v) high level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i oh = -4 ma i oh = -8ma i oh = -12 ma v dd -0.4 v v oh (3.3v) low level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i ol = -2 ma i ol = -4 ma i ol = -6 ma v dd -0.3 v v oh (3.0v) high level output voltage type 1 - ts1d2, co1 type 2 - ts2, co2 type 3 - ts3, co3, co3s v dd = min i oh = -1.8 ma i oh = -3.5 ma i oh = -5 ma v dd -0.3 v i oz output leakage current -- -1 1 a c out output pin capacitance f =1 mhz, v dd = 0v 12 pf c bid bidirectional pin capacitance f =1 mhz, v dd = 0v 12 pf table 6-3: input specifications (continued) symbol parameter condition min typ max units
epson research and development page 29 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 7 a.c. characteristics conditions : v dd = 3.0v 10%, v dd = 3.3v 10%, or v dd = 5.0v 10% t a = -40 c to 85 c t rise and t fall for all inputs must be < 5 nsec (10% ~ 90%) c l = 80pf (bus/mpu interface) c l = 100pf (lcd panel interface) c l = 20pf (display memory interface) 7.1 bus interface timing 7.1.1 mc68000 interface timing note all input timing parameters are based on a maximum 16mhz mpu clock. iow# timing figure 10: iow# timing (mc68000) table 7-1: iow# timing (mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[9:1] valid before as# falling edge 10 0 ns t2 ab[9:1] hold from as# rising edge 20 10 ns t3 iocs# hold from as# rising edge 00 ns t4 uds#/lds# valid before as# rising edge 30 20 ns t5 uds#/lds# falling edge to dtack# falling edge 40 25 ns t6 as# rising edge to dtack# hi-z delay 40 25 ns t7 db[15:0] setup to as# rising edge 20 10 ns t8 db[15:0] hold from as# rising edge 20 10 ns ab[9:1] as# uds#/lds# va lid val id t2 t6 t3 t1 db[15:0] r/w dtack# t5 t4 iocs# t7 t8 hi-z hi-z hi-z hi-z invalid
page 30 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 ior# timing figure 11: ior# timing (mc68000) table 7-2: ior# timing (mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[9:1] and iocs# valid before as# falling edge 10 0 ns t2 ab[9:1] and iocs# hold from as# rising edge 20 10 ns t3 as# falling edge to dtack# falling edge 40 25 ns t4 as# rising edge to dtack# hi-z delay 40 25 ns t5 as# falling edge to db[15:0] valid 60 40 ns t6 db[15:0] hold from as# rising edge 20 15 ns t7 as# rising edge to db[15:0] hi-z delay 35 25 ns ab[9:1] as# r/w# valid valid t2a t3 t7 t1 db[15:0] iocs# uds#/lds# t4 t5 t6 dtack# hi-z hi-z hi-z hi-z t2b invalid
epson research and development page 31 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 memw# timing figure 12: memw# timing (mc68000) where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3) table 7-3: memw# timing (mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[19:1] and memcs# valid before as# falling edge 00ns t2 ab[19:1] and memcs# hold from as# rising edge 00ns t3 as# falling edge to dtack# falling edge 3.5 * mclk + 20 3.5 * mclk + 10 ns t4 as# rising edge to dtack hi-z delay 40 25 ns t5 as# falling edge to db[15:0] valid mclk -40 mclk -20 ns t6 db[15:0] hold from as# rising edge 00ns ab[19:1] as# uds#/lds# valid valid t1 t3 t6 t2 t5 t4 db[15:0] memcs# r/w# dtack# hi-z hi-z hi-z hi-z invalid
page 32 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 memr# timing figure 13: memr# timing (mc68000) where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3) table 7-4: memr# timing (mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[19:1] and memcs# valid before as# falling edge 00ns t2 ab[19:1] and memcs# hold from as# rising edge 00ns t3 as# falling edge to dtack# falling edge 3.5 * mclk + 20 3.5 * mclk + 10 ns t4 as# rising edge to dtack# hi-z delay 40 15 ns t5 dtack# falling edge to db[15:0] valid 20 15 ns t6 db[15:0] hold from as# rising edge 25 15 ns t7 as# rising edge to db[15:0] hi-z delay 40 30 ns ab[19:1] as# uds#/lds# dtack# valid val id t1 t3 t7 t5 t2 t6 t4 db[15:0] memcs# r/w# hi-z hi-z hi-z hi-z invalid
epson research and development page 33 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 7.1.2 non-mc68000, mpu/bus with ready (or wait#) signal iow# timing figure 14: iow# timing (non-mc68000) table 7-5: iow# timing (non-mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[9:0], bhe# and iocs# valid before iow# falling edge 10 0 ns t2 ab[9:0], bhe# and iocs# hold from iow# rising edge 20 10 ns t3 db[15:0] setup to iow# rising edge 20 10 ns t4 db[15:0] hold from iow# rising edge 20 10 ns t5 pulse width of iow# 30 20 ns ab[9:0] iocs# iow# val id valid t2 t4 t3 t1 db[15:0] bhe# t5 hi-z hi-z
page 34 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 ior# timing figure 15: ior# timing (non-mc68000) table 7-6: ior# timing (non-mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[9:0], bhe# and iocs# valid before ior# falling edge 10 0 ns t2 ab[9:0], bhe# and iocs# hold from ior# rising edge 20 10 ns t3 ior# falling edge to db[15:0] valid 60 40 ns t4 db[15:0] hold from ior# rising edge 20 15 ns t5 ior# rising edge to db[15:0] hi-z delay 35 25 ns ab[9:0] iocs# ior# va lid valid t2 t4 t5 t3 t1 db[15:0] bhe# hi-z hi-z
epson research and development page 35 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 memw# timing figure 16: memw# timing (non-mc68000) where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3) table 7-7: memw# timing (non-mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[19:0], bhe# and memcs# valid before memw# falling edge 00ns t2 ab[19:0], bhe# and memcs# hold from memw# rising edge 00ns t3 memw# falling edge to ready falling edge 30 20 ns t4 memw# falling edge to db[15:0] valid mclk -40 mclk -20 ns t5 db[15:0] hold from memw# rising edge 00ns t6 ready negated pulse width 3.5* mclk + 20 3.5* mclk + 10 ns ab[19:0] memcs# memw# ready valid valid t1 t3 t6 t2 t5 t4 db[15:0] bhe# hi-z hi-z hi-z hi-z
page 36 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 memr# timing figure 17: memr# timing (non-mc68000) where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3.) table 7-8: memr# timing (non-mc68000) 3v/3.3v 5v symbol parameter min max min max units t1 ab[19:0], bhe# and memcs# valid before memr# falling edge 00ns t2 ab[19:0], bhe# and memcs# hold from memr# rising edge 00ns t3 memr# falling edge to ready falling edge 30 20 ns t4 ready rising edge to db[15:0] valid 15 10 ns t5 db[15:0] hold from memr# rising edge 20 10 ns t6 memr# rising edge to db[15:0] hi-z delay 30 20 ns t7 ready negated pulse width 3.5* mclk + 20 3.5* mclk + 10 ns ab[19:0] memcs# memr# ready va lid valid t1 t3 t7 t5 t2 t6 t4 db[15:0] bhe# hi-z hi-z hi-z hi-z
epson research and development page 37 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 7.2 clock input requirements figure 18: clock input requirements table 7-9: clock input requirements symbol parameter min typ max units t osc input clock period (clki) 40 ns t pwh input clock pulse width high (clki) 40% 60% t osc t pwl input clock pulse width low (clki) 40% 60% t osc t f input clock fall time (10% - 90%) 5ns t r input clock rise time (10% - 90%) 5ns t pwl t pwh t f clock input waveform t r t osc v ih v il 10% 90%
page 38 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.2.1 recommended clock input the nominal frequency must be calculated based on the formulas found in frame rate calculation on page 84. the crystal oscillator must be ?fundamental mode? and have the following recommended rc load values: r l = 2m ? 5% c l = 6.8 pf the figure below demonstrates both a crystal interface and an oscillator interface to the s1d13503. figure 19: recommended clock interface s1d13503 92 93 r l x1 c l c l s1d13503 92 93 out gnd v cc nc v cc crystal interface oscillator interface x1
epson research and development page 39 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 7.3 display memory interface timing 7.3.1 write data to display memory figure 20: write data to display memory where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3.) table 7-10: write data to display memory 3v/3.3v 5v symbol parameter min max min max units t1 address cycle time mclk - 15 mclk - 10 ns t2 va[15:0], vcs0# and vcs1# valid before vwe# falling edge 00ns t3 va[15:0], vcs0# and vcs1# hold from vwe# rising edge 00ns t4 pulse width of vwe# mclk - 15 mclk - 10 ns t5 vd[15:0] setup to vwe# rising edge mclk - 20 mclk - 15 ns t6 vd[15:0] hold from vwe# rising edge 00ns va[15:0] vcs0#, vcs1# vwe# output input input voe# t1 t2 t3 t4 t5 t6 vd[15:0] valid hi-z hi-z hi-z hi-z
page 40 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.3.2 read data from display memory figure 21: read data from display memory where mclk period = 1/f osc , or 2/f osc , or 4/f osc depending on which display mode the chip is in. (see section 9.2 and 9.3.) table 7-11: read data from display memory 3v/3.3v 5v symbol parameter min max min max t1 address cycle time mclk - 15 mclk - 10 t2 va[15:0], vcs0# and vcs1# access time mclk - 40 mclk - 25 t3 vd[15:0] hold time 00 va[15:0] vcs0#, vcs1# input input input t1 t2 t3 vd[15:0] valid
epson research and development page 41 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 7.4 lcd interface 7.4.1 lcd interface timing - 4-bit single, 8-bit single/dual monochrome panels figure 22: lcd interface timing - monochrome panel yd s1d13503 outputs t1 t2 t4 t3 lp wf lp xscl (aux[01] bit 5 = 0) xscl (aux[01] bit 5 = 1) t7a t8 t9 t5 t6a t10 t12 t11 ud[3:0] ld[3:0] t13 t7b t8 t9 t10 t11 ud[3:0] ld[3:0] t12 12 12 s1d13503 outputs t6b, t6c 80 lp s1d13503 outputs
page 42 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 table 7-12: lcd interface timing - 4-bit single and 8-bit single/dual monochrome panel 4-bit single 8-bit single/dual symbol parameter min max min max units t1 lp period (single panel mode) ht + hndp - 10 ht + hndp - 10 ns t1 lp period (dual panel mode) n/a 2(ht + hndp) - 10 ns t2 yd hold from lp falling edge (aux[01] bit 5 = 0) 8t osc - 10 8t osc - 10 ns t2 yd hold from lp falling edge (aux[01] bit 5 = 1) 13t osc - 10 13t osc - 10 ns t3 lp pulse width (aux[01] bit 5 = 0) 6t osc - 5 6t osc - 5 ns t3 lp pulse width (aux[01] bit 5 = 1) 5t osc - 5 5t osc - 5 ns t4 wf delay from lp falling edge 0 20 0 20 ns t5 lp setup to xscl falling edge (aux[01] bit 5 = 0 and aux[03] bit 2 = 0) n/a 2t osc - 5 ns t6a lp hold from xscl falling edge (aux[01] bit 5 = 0 and aux[03] bit 2 = 0) 2t osc - 5 4t osc - 5 ns t6a lp hold from xscl falling edge (aux[01] bit 5 = 0 and aux[03] bit 2 = 1) t osc - 5 2t osc - 5 ns t6b xscl falling edge to lp falling edge - single panel mode (aux[01] bit 5 = 1 and aux[03] bit 2 = 0) 13t osc - 5 15t osc - 5 ns t6b xscl falling edge to lp falling edge - single panel mode (aux[01] bit 5 = 1 and aux[03] bit 2 = 1) 12t osc - 5 13t osc - 5 ns t6c xscl falling edge to lp falling edge - dual panel mode (aux[01] bit 5 = 1 and aux[03] bit 2 = 0) n/a 31t osc - 5 ns t6c xscl falling edge to lp falling edge - dual panel mode (aux[01] bit 5 = 1 and aux[03] bit 2 = 1) n/a 29t osc - 5 ns t7a lp falling edge to xscl falling edge (aux[01] bit 5 = 0 and aux[03] bit 2 = 0) 2t osc - 5 4t osc - 5 ns t7a lp falling edge to xscl falling edge (aux[01] bit 5 = 0 and aux[03] bit 2 = 1) t osc - 5 2t osc - 5 ns t7b lp falling edge to xscl falling edge (aux[01] bit 5 = 1 and aux[03] bit 2 = 0) 7t osc - 5 9t osc - 5 ns t7b lp falling edge to xscl falling edge (aux[01] bit 5 = 1 and aux[03] bit 2 = 1) 6t osc - 5 7t osc - 5 ns t8 xscl period (aux[03] bit 2 = 0) 4t osc - 5 8t osc - 5 ns t8 xscl period (aux[03] bit 2 = 1) 2t osc - 5 4t osc - 5 ns t9 xscl high width (aux[03] bit 2 = 0) 2t osc - 5 4t osc - 5 ns t9 xscl high width (aux[03] bit 2 = 1) t osc - 5 2t osc - 5 ns t10 xscl low width (aux[03] bit 2 = 0) 2t osc - 10 4t osc - 10 ns t10 xscl low width (aux[03] bit 2 = 1) t osc - 10 2t osc - 10 ns t11 ud[3:0], ld[3:0] setup to xscl falling edge (aux[03] bit 2 = 0) 2t osc - 10** 4t osc - 10** ns
epson research and development page 43 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 where t osc = 1/f osc = input (pixel) clock period, where ht = (number of horizontal panel pixels) * t osc , where hndp = horizontal non-display period in units of t osc (see section 9.3 on page 84 for details). ** -10 ns for 5v operation, - 24 ns for 3.0v and 3.3v operation. t11 ud[3:0], ld[3:0] setup to xscl falling edge (aux[03] bit 2 = 1) t osc - 10** 2t osc - 10** ns t12 ud[3:0], ld[3:0] hold from xscl falling edge (aux[03] bit 2 = 0) 2t osc - 10 4t osc - 10 ns t12 ud[3:0], ld[3:0] hold from xscl falling edge (aux[03] bit 2 = 1) t osc - 10 2t osc - 10 ns t13 lp falling edge to xscl rising edge (aux[01] bit 5 = 1) 5t osc - 5 5t osc - 5 ns table 7-12: lcd interface timing - 4-bit single and 8-bit single/dual monochrome panel
page 44 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.4.2 lcd interface timing - 4-bit single color panel figure 23: lcd interface timing - 4-bit single color panel t4 t1 lp t2 t3 t6 t13 t7 t10 t9 t8 123 t11 t12 yd lp xscl ud 4 t5 wf
epson research and development page 45 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table 7-13: lcd interface timing - 4-bit single color panel where t osc = 1/f osc = input (pixel) clock period, where ht = (number of horizontal panel pixels) * t osc , where hndp = horizontal non-display period in units of t osc (see section 9.3 on page 84 for details). ** 5v operation, for 3.0v and 3.3v operation t11 will be 0.5t osc - 24. symbol parameter min typ max units t1 lp period ht + hndp - 10 ns t2 yd hold from lp falling edge 13t osc - 10 ns t3 lp pulse width 5t osc - 5 ns t4 wf delay from lp falling edge 020ns t5 lp setup to xscl falling edge 19t osc - 5 ns t6 xscl falling edge to lp falling edge 20t osc - 5 ns t7 lp falling edge to xscl falling edge 14t osc - 5 ns t8 xscl period t osc - 5 ns t9 xscl high width 0.5t osc - 5 ns t10 xscl low width 0.5t osc - 5 ns t11 ud setup to xscl falling edge 0.5t osc - 10** ns t12 ud hold from xscl falling edge 0.5t osc - 10 ns t13 lp falling edge to xscl rising edge 13.5t osc - 10 ns
page 46 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.4.3 lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels figure 24: lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels t1 lp t2 t3 t6 t7 t5 t8 t10 t9 123 t12 t11 yd lp xscl ud/ld 4 t13 t4 wf
epson research and development page 47 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table 7-14: lcd interface timing - 8-bit single color panels format 2/8-bit dual color panels where t osc = 1/f osc = input (pixel) clock period, where ht = (number of horizontal panel pixels) * t osc , where hndp = horizontal non-display period in units of t osc (see section 9.3 on page 84 for details). ** 5v operation, for 3.0v and 3.3v operation t11 will be 1.5t osc - 24. symbol parameter min typ max units t1 lp period (single panel mode) ht + hndp - 10 ns t1 lp period (dual panel mode) 2(ht + hndp) - 10 ns t2 yd hold from lp falling edge 13t osc - 10 ns t3 lp pulse width 5t osc - 5 ns t4 wf delay from lp falling edge 020ns t5 lp setup to xscl falling edge 19.5t osc - 5 ns t6 xscl falling edge to lp falling edge (single panel mode) 20t osc - 5 ns t6 xscl falling edge to lp falling edge (dual panel mode) 52t osc - 5 ns t7 lp falling edge to xscl falling edge 14.5t osc - 5 ns t8 xscl period 2.5t osc - 5 ns t9 xscl high width t osc - 5 ns t10 xscl low width 1.5t osc - 5 ns t11 ud/ld setup to xscl falling edge 1.5t osc - 10** ns t12 ud/ld hold from xscl falling edge t osc - 5 ns t13 lp falling edge to xscl rising edge 13.5t osc - 10 ns
page 48 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.4.4 lcd interface timing - 16-bit single/dual color panels figure 25: lcd interface timing - 16-bit single/dual color panels t1 lp t2 t3 t6 t13 t7 t10 t9 t8 123 t11 t12 yd lp xscl ud/ld 4 t5 t14 t15 wf t4
epson research and development page 49 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table 7-15: lcd interface timing - 16-bit single/dual color panels where t osc = 1/f osc = input (pixel) clock period, where ht = (number of horizontal panel pixels) * t osc , where hndp = horizontal non-display period in units of t osc (see section 9.3 on page 84 for details). ** 5v operation, for 3.0v and 3.3v operation t11 will be 1.5t osc - 24. symbol parameter min typ max units t1 lp period (single panel mode) ht + hndp - 10 ns t1 lp period (dual panel mode) 2(ht + hndp) - 10 ns t2 yd hold from lp falling edge 13t osc - 10 ns t3 lp pulse width 5t osc - 5 ns t4 wf delay from lp falling edge 020ns t5 lp setup to xscl falling edge 22t osc - 5 ns t6 xscl falling edge to lp falling edge (single panel mode) 20t osc - 5 ns t6 xscl falling edge to lp falling edge (dual panel mode) 52t osc - 5 ns t7 lp falling edge to xscl falling edge 17t osc - 5 ns t8 xscl period 5t osc - 5 ns t9 xscl high width 2t osc - 5 ns t10 xscl low width 3t osc - 10 ns t11 ud/ld setup to xscl falling edge 1.5t osc - 10** ns t12 ud/ld hold from xscl falling edge t osc - 5 ns t13 lp falling edge to xscl rising edge 15t osc - 10 ns t14 ud/ld setup to xscl rising edge 1.5t osc - 10 ns t15 ud/ld hold from xscl rising edge 0.5t osc - 5 ns
page 50 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.4.5 lcd interface timing - 8-bit single color panels format 1 figure 26: lcd interface timing - 8-bit single color panels format 1 t1 lp t2 t3 t7a t14b t7b t8b t6b t9b t11b t10b t6a t14a t8a t11a t10a t9a 123 t13b t12a t13a t12b yd lp xscl2 xscl ud/ld (wf)
epson research and development page 51 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 table 7-16: lcd interface timing - 8-bit single color panels format 1 where t osc = 1/f osc = input (pixel) clock period, where ht = (number of horizontal panel pixels) * t osc , where hndp = horizontal non-display period in units of t osc (see section 9.3 on page 84 for details). ** 5v operation, for 3.0v and 3.3v operation t12 will be 1.5t osc - 24. symbol parameter min typ max units t1 lp period ht + hndp - 10 ns t2 yd hold from lp falling edge 13t osc - 10 ns t3 lp pulse width 5t osc - 5 ns t6a lp setup to xscl falling edge 22t osc - 5 ns t6b lp setup to xscl2 falling edge 19.5t osc - 5 ns t7a xscl falling edge to lp falling edge 20t osc - 5 ns t7b xscl2 falling edge to lp falling edge 23.5t osc - 5 ns t8a lp falling edge to xscl falling edge 17t osc - 5 ns t8b lp falling edge to xscl2 falling edge 14.5t osc - 5 ns t9a xscl period 4t osc - 5 ns t9b xscl2 period 4t osc - 5 ns t10a xscl high width t osc - 5 ns t10b xscl2 high width t osc - 5 ns t11a xscl low width 3t osc - 10 ns t11b xscl2 low width 3t osc - 10 ns t12a ud/ld setup to xscl falling edge 1.5t osc - 10** ns t12b ud/ld setup to xscl2 falling edge 1.5t osc - 10** ns t13a ud/ld hold from xscl falling edge t osc - 5 ns t13b ud/ld hold from xscl2 falling edge t osc - 5 ns t14a lp falling edge to xscl rising edge 16t osc - 10 ns t14b lp falling edge to xscl2 rising edge 13.5t osc - 10 ns
page 52 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 7.4.6 lcd interface options figure 27: 4-bit single monochrome panel timing lp : 240 pulses lp xscl ud[3:0] line1 line2 line3 line4 line239 line240 yd line1 line2 lp: 4 pulses lp wf ud2 1-2 1-6 1-318 ud1 1-3 1-7 1-319 ud0 1-4 1-8 1-320 ud3 1-1 1-5 1-317 wf xscl: 80 clock periods example timing for a 320x240 single panel
epson research and development page 53 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 28: 8-bit single monochrome panel timing lp : 480 pulses lp xscl ud[3:0], ld[3:0] line1 line2 line3 line4 line479 line480 yd line1 line2 lp wf ud2 1-2 1-10 1-634 ud1 1-3 1-11 1-635 ud0 1-4 1-12 1-636 ld3 1-5 1-13 1-637 ld2 1-6 1-14 1-638 ld1 1-7 1-15 1-639 ld0 1-8 1-16 1-640 ud3 1-1 1-9 1-633 wf lp: 4 pulses example timing for a 640x480 panel xscl:80 clock periods
page 54 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 29: 8-bit dual monochrome panel timing lp : 240 pulses lp xscl ud[3:0], ld[3:0] line1/241 line2/242 line3/243 line4/244 line 239/479 line240/480 yd lp wf ud2 1-2 1-6 1-638 ud1 1-3 1-7 1-639 ud0 1-4 1-8 1-640 ld3 241-1 241-5 241-637 ld2 241-638 ld1 241-639 ld0 241-640 ud3 1-1 1-5 1-637 xscl: 160 clock periods wf 241-2 241-6 241-3 241-7 241-4 241-8 lp: 2 pulses example timing for a 640x480 panel line1/241 line2/242
epson research and development page 55 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 30: 4-bit single color panel timing lp : 240 pulses lp xscl ud[3:0] line1 line2 line3 line4 line239 line240 yd line1 line2 lp ud2 1-g1 1-b2 1-r320 ud1 1-b1 1-r3 1-g320 ud0 1-r2 1-g3 1-b320 ud3 1-r1 1-g2 1-b319 xscl: 240 clock periods 1-r4 1-g4 1-b4 1-b3 example timing for a 320x240 panel lp: 4 pulses wf wf
page 56 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 31: 8-bit single color panel timing - format 1 : aux[03] bit 3 = 0 and aux[01] bit 2 = 1 yd lp ud[3:0] lp xscl2 ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 lp: 480 pulses xscl: 120 clock periods line1 line480 line2 line3 line4 line479 line1 line2 1-g1 1-r2 1-b2 1-g3 1-r4 1-b4 1-g5 1-r6 1-r636 1-b636 1-g637 1-r638 1-b638 1-g639 1-r640 1-b640 ld[3:0] 1-g6 1-r7 1-b7 1-g8 1-r9 1-b9 1-g10 1-r11 1-r12 1-b12 1-g13 1-r14 1-b14 1-g15 1-r16 1-b16 1-b6 1-g7 1-r8 1-b8 1-g9 1-r10 1-b10 1-g11 1-b11 1-g12 1-r13 1-b13 1-g14 1-r15 1-b15 1-g16 1-b635 1-g636 1-r637 1-b637 1-g638 1-r639 1-b639 1-g640 1-r1 1-b1 1-g2 1-r3 1-b3 1-g4 1-r5 1-b5 xscl2: 120 clock periods xscl example timing for a 640x480 panel lp: 4 pulses
epson research and development page 57 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 32: 8-bit single color panel timing - format 2 : aux[03] bit 3 = 1 and aux[01] bit 2 = 1 lp : 240 pulses lp xscl line1 line2 line3 line4 line239 line240 yd line1 line2 lp ud2 1-g1 1-r4 1-b318 ud1 1-b1 1-g4 ud0 1-r2 1-b4 1-g319 ud3 1-r1 1-b3 1-g318 xscl: 120 clock periods 1-b6 1-r7 1-g7 1-g6 1-b2 1-g5 1-r320 1-r3 1-b5 1-g320 1-g3 1-r6 1-b320 1-g2 1-r5 1-b319 1-r8 1-g8 1-b8 1-b7 ld3 ld2 ld1 ld0 1-r319 example timing for a 320x240 panel ld[3:0] ud[3:0] lp: 4 pulses wf wf
page 58 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 33: 8-bit dual color panel timing figure 34: external circuit required for 16-bit panel yd lp ud[3:0] lp xscl ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 lp: 240 pulses xscl: 480 clock periods 241-r1 line241 line480 line242 line243 line244 line479 line241 line242 241-g1 241-b1 241-r2 241-b3 241-r4 241-g4 241-b4 ld[3:0] line1 line240 line2 line3 line4 line239 line1 line2 241-g2 241-b2 241-r3 241-g3 1-r637 1-g637 1-b637 1-r638 1-b639 1-r640 1-g640 1-b640 1-g638 1-b638 1-r639 1-g639 1-r1 1-g1 1-b1 1-r2 1-b3 1-r4 1-g4 1-b4 1-g2 1-b2 1-r3 1-g3 241-r637 241-g637 241-b637 241-r638 241-b639 241-r640 241-g640 241-b640 241-g638 241-b638 241-r639 241-g639 example timing for a 640x480 panel lp: 2 pulses wf wf ud[3:0] ld[3:0] xscl ud[3:0] ld[3:0] ud[7:4] ld[7:4] to 16-bit panel from s1d13503 d q ck
epson research and development page 59 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 35: 16-bit single color panel timing with external circuit lp : 480 pulses lp xscl pixel data line1 line2 line3 line4 line479 line480 yd line1 line2 lp ud2 ud1 ud0 ud3 xscl: 120 clocks 1-r1 1-b3 1-b1 1-g4 1-g2 1-r5 1-r3 1-b5 ud6 ud5 ud4 ud7 ld3 ld2 ld1 ld0 1-g1 1-r4 1-r2 1-b4 1-b2 1-g5 1-g3 1-r6 ld6 ld5 ld4 ld7 1-b3 1-g4 1-r5 1-b5 ud3 ud2 ud1 ud0 1-r4 1-b4 1-g5 1-r6 ld3 ld2 ld1 ld0 16-bit panel inputs 1-r1 1-b1 1-g2 1-r3 1-b635 1-g636 1-r637 1-b637 1-b638 1-g639 1-r640 1-b640 1-g638 1-r639 1-b639 1-g640 1-g1 1-r2 1-b2 1-g3 1-r636 1-b636 1-g637 1-r638 1-g638 1-r639 1-b639 1-g640 1-b638 1-g639 1-r640 1-b640 1-r636 1-b636 1-g637 1-r638 1-b635 1-g636 1-r637 1-b637 s1d13503 outputs example timing for a 640x480 panel lp: 4 pulses wf wf
page 60 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 36: 16-bit dual color panel timing with external circuit lp : 240 pulses lp xscl pixel data line1/241 yd lp ud2 ud1 ud0 ud3 xscl: 240 clocks 1-r1 1-b3 1-g1 1-b2 1-b1 1-r3 1-r2 1-g3 ud6 ud5 ud4 ud7 ld3 ld2 ld1 ld0 241-r1 ld6 ld5 ld4 ld7 1-g2 1-b2 1-r3 1-g3 ud3 ud2 ud1 ud0 ld3 ld2 ld1 ld0 16-bit panel inputs 1-r1 1-g1 1-b1 1-r2 1-g638 1-b638 1-r639 1-g639 241- b639 1-b639 1-r640 1-g640 1-b640 241-r1 241-g638 1-b639 1-r640 1-g640 1-b640 241- b639 1-g2 1-r4 1-g4 1-b4 1-g638 1-b638 1-r639 1-g639 241-g2 241-b3 241-g1 241-b2 241-r4 241-b1 241-r3 241-b4 241-r2 241-g3 241-b4 241- g638 241- r640 241- b638 241- g640 241- r639 241- b640 241- g639 241-g1 241-b1 241-r2 241-g2 241-b2 241-r3 241-g3 241-b638 241-r639 241-g639 241- r640 241- g640 241- b640 line2/242 line3/243 line4/244 line239/479 line240/480 line1/241 line2/242 s1d13503 outputs example timing for a 640x480 panel lp: 2 pulses wf wf
epson research and development page 61 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 8 hardware register interface the s1d13503 is configured and controlled via 16 internal 8-bit registers. there are two ways to map these registers into the system i/o space. 1. direct-mapping: absolute i/o address = system address lines ab[3:0] + base i/o mapped address (where base i/o address is selected by vd7-vd12, see table 5-6) this scheme requires 16 sequential i/o addresses starting from the i/o mapped base address selected by vd7-vd12 (see table 5-6). to perform an i/o access: write data iow {absolute i/o address}, {data} read data ior {absolute i/o address} 2. indexing: i/o address = internal index register bits [3:0] this scheme requires 2 sequential i/o addresses starting from the base address selected by vd4-vd12 (see table 5-6). to perform an 8-bit i/o access: write index iow {i/o mapped address}, {index} ; write the index of the register to be accessed then write data iow {i/o mapped address +1}, {data} ; write data to the indexed register or read data ior {i/o mapped address +1} ; read the indexed register to perform a 16-bit i/o access: write data iow {i/o mapped address}, {index,data} ; write the index and data of the register to be accessed read data iow {i/o mapped address}, {index} ; write to the indexed register ior {i/o mapped address +1} ; read the indexed register 8.1 register descriptions bit 7 test mode enable when this bit = 0 normal operation is enabled. when this bit = 1 the chip is placed in a special test mode. the test input bits and test output bits (bits 6:0) are used to select various internal test functions. bit 6 reserved during normal operation this bit must = 0. bits 5-0 test mode input and output bits [2:0] when bit 7 = 1 these are the test input select input and output bits. when bits 6 and 7 = 0 (normal opera- tion) these bits may be used as read/write scratch registers. aux[00] test register i/o address = 0000b, read/write test mode enable reserved test input select bit 2 test input select bit 1 test input select bit 0 test output select bit 2 test output select bit 1 test output select bit 0
page 62 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 bit 7 disp this bit selects display on or off. when this bit = 0, display off is selected (ld0-3 and ud0-3 are forced to 0 ). when this bit = 1, display on is selected. this bit goes low on reset. bit 6 panel this bit selects the lcd panel configuration (single or dual). when this bit = 0, single lcd panel drive is selected. when this bit = 1 dual lcd panel drive is selected. this bit goes low on reset. bit 5 mask xscl xscl is automatically masked during the horizontal non-display period if any of the following criteria is met: aux[0c] value is greater than 00h. color panel is selected. this bit (aux[01] bit 5) = 1. . xscl will not be masked during the horizontal non-display period if color panel is not selected, aux[0c] = 00h and this bit = 0. bit 4 lcde the state of this pin determines the state of output pin 82, lcdenb, and is intended for control of an external lcdbias power supply. however, this pin can be used as a general i/o pin if desired. when lcde = 0, lcdenb is forced low. when lcde = 1, lcdenb is forced high. lcde goes low on reset. bit 3 gray shade/color in gray shade display modes, this bit selects between 16-level or 4-level gray shade display. when this bit = 1, 16 gray shades are displayed (4 bits/pixel). when this bit = 0, 4 gray shades of a possible 16 are dis- played (2 bits/pixel). in color display modes, this bit selects between 16 color or 4 color display. when this bit = 1, 16 colors are displayed out of a possible of 4096 colors (4 bits/pixel). when this bit = 0, 4 colors are displayed out of a possible of 4096 colors (2 bits/pixel). this bit is ignored when either black-and-white (bw) or 256 color mode is selected (aux[03] bit 2 = 1). this bit goes low on reset. aux[01] mode register 0 i/o address = 0001b, read/write. disp panel mask xscl lcde gray shade / color lcd data width bit 0 memory interface rams table 8-1: gray shade/color mode selection display modes gray shade/ color aux[01] bit 3 bw/ 256 colors aux[03] bit 2 color mode aux[03] bit 1 256 colors don?t care 1 1 16 colors101 4 colors001 16 grays 1 0 0 4 grays000 bw don?t care 1 0
epson research and development page 63 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 bit 2 lcd data width bit 0 together with lcd data width bit 1 (aux[03] bit 3) this bit selects different display data formats. the following table shows the function of these two bits: for 8-bit dual panels, the data transfer width is forced to 4 bits per panel. this bit goes low on reset. bit 1 memory interface this bit selects between the 8-bit or 16-bit memory interface. when this bit = 0, the 16-bit memory inter- face is selected. when this bit = 1, the 8-bit memory interface is selected. if 16-bit bus interface (vd0 = 1 on reset) or 256 color mode (aux[03] bits 2-1 = 11) is selected, the memory interface bit is forced to 0 internally (16-bit). this bit goes low on reset. bit 0 rams this bit configures the display memory address lines for an 8-bit memory interface system. when this bit = 0, addressing for 8kx8 sram on an 8-bit display memory data bus interface is selected. when this bit = 1, addressing for 32kx8 sram on an 8-bit display memory data bus interface is selected. this bit goes low on reset. this bit is ignored for a 16-bit memory interface. bits 7-0 line byte count bits [7:0] along with line byte count bit 8 (aux[03] bit 0), this is the number of bytes to be fetched per display line minus 1. to calculate the line byte count use the following formula: example: to calculate the line byte count for 640 horizontal pixels with 16 gray shades (4 bits-per-pixel) and 16-bit memory interface: table 8-2: lcd data width panel lcd data width bit 1 aux[03] bit 3 lcd data width bit 0 aux[01] bit 2 function monochrome don?t care 0 4-bit lcd data width monochrome don?t care 1 8-bit lcd data width color 0 0 4-bit lcd data width color 0 1 8-bit lcd data width - format 1 color 1 0 16-bit lcd data width (with external circuit) color 1 1 8-bit lcd data width - format 2 aux[02] line byte count register (lsb) i/o address = 0010b, read/write. line byte count bit 7 line byte count bit 6 line byte count bit 5 line byte count bit 4 line byte count bit 3 line byte count bit 2 line byte count bit 1 line byte count bit 0 linebytecount decimal () bitsperpixel memoryinterfacewidth -------------------------------------------------------------- horizontalresolution ?? ?? 1 ? = linebytecount decimal () 4 bitsperpixel 16 bits ------------------------------------- 640 1 159 = ? =
page 64 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 the following two tables summarize the maximum value of the line byte count register for different display modes and display memory interface. bits 7-6 ps bits [1:0] selects the power save modes as shown in the following table. the ps bits [1:0] go low on reset. refer to power save modes on page 77 for a complete power save mode description. bit 5 lcd signal state when this bit = 0, all lcd interface signals are forced low during power save modes. when this bit = 1, all lcd interface signals are forced to a high impedance (hi-z) state during power save modes. this bit goes low on reset. bit 4 lut bypass when the lut bypass bit = 0, the look-up table is used for display data output in gray shade modes. when this bit = 1, the look-up table is bypassed for display data output in gray shade modes (for power save purposes). there is no effect on changing this bit in bw and color modes. in bw display mode, the look-up table is always bypassed and in color display mode the look-up table cannot be bypassed. the lut bypass bit goes low on reset. table 8-3: maximum value of line byte count register - 8-bit display memory interface display modes maximum value of line byte count register corresponding maximum number of pixels in one display line black-and-white (bw) 0ffh 256 x 8 = 2048 4-level gray shade / 4 colors 0ffh 256 x 4 = 1024 16-level gray shade / 16 colors 1ffh 512 x 2 = 1024 table 8-4: maximum value of line byte count register - 16-bit display memory interface display modes maximum value of line byte count register corresponding maximum number of pixels in one display line black-and-white (bw) 0ffh 256 x 16 = 4096 4-level gray shade / 4 colors 0ffh 256 x 8 = 2048 16-level gray shade / 16 colors 0ffh 256 x 4 = 1024 256 colors 1ffh 512 x 2 = 1024 aux[03] mode register 1 i/o address = 0011b, read/write ps bit 1 ps bit 0 lcd signal state lut bypass lcd data width bit 1 bw / 256 colors color mode line byte count bit 8 table 8-5: power save mode selection ps1 ps0 mode activated 0 0 normal operation 0 1 power save mode 1 1 0 power save mode 2 11 reserved
epson research and development page 65 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 bit 3 lcd data width bit 1 together with lcd data width bit 0 (aux[01] bit 2), this bit selects different display data formats. see table 8-2, ?lcd data width,? on page 63 for details. this bit goes low on reset. bit 2 bw / 256 colors in bw/gray shade display modes, when this bit = 1, black-and-white (bw) mode is selected. when this bit = 0, either 4-level gray shade mode or 16-level gray shade mode is selected. in color display modes, when this bit = 1, 256 color mode is selected. when this bit = 0, either 4 color mode or 16 color mode is selected. see table 8-1, ?gray shade/color mode selection,? on page 62 for details. this bit goes low on reset. bit 1 color mode when this bit = 1, color display modes are selected. when bit = 0, bw/gray shade display modes are selected. see table 8-1, ?gray shade/color mode selection,? on page 62 for details. this bit goes low on reset. bit 0 line byte count bit 8 this is the msb of the number of bytes to be fetched per display line minus 1 (see aux[02]). this bit only has effect when in either 16 colors/gray shades with 8-bit memory interface or 256 colors with 16-bit memory interface. . bits 7-0 total display line count bits [7:0] these are the 8 lsb of the 10 bit total display line count and represent the number of scan lines -1, to a maximum value of 3ffh or 1024 scan lines. in single panel mode: in dual panel mode: note that the value programmed partially determines the frame period, and hence affects display duty cycle. bits 8 and 9 are located in the following register (aux[05]). aux[04] total display line count register (lsb) (vertical total) i/o address = 0100b, read/write. total disp. line count bit 7 total disp. line count bit 6 total disp. line count bit 5 total disp. line count bit 4 total disp. line count bit 3 total disp. line count bit 2 total disp. line count bit 1 total disp. line count bit 0 totaldisplaylinecount numberofdisplaylines 1 ? = totaldisplaylinecount numberofdisplaylines 2 --------------------------------------------------------------- ?? ?? 1 ? =
page 66 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 . bits 7-2 wf count bits [5:0] these bits are used to adjust the wf output signal period. the binary value stored in these bits represents the number of lp pulses -1 between toggles of the wf output. the power up reset value of these bits is 0, which causes the wf output to toggle every frame. when values of 01h to 3fh are programmed into these bits, the results are wf toggling every 1+n lp pulses, where n is the value programmed. these bits have no effect when 8-bit single color panel format 1 is selected. bits 1-0 total display line count bits [9:8] these bits are the two msb of the total display line count register (aux[04]). aux[06] bits 7-0 screen 1 display start address bits [15:0] aux[07] bits 7-0 these 16 bits determine the screen 1 display start address. in an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). in a 16-bit memory configuration these are the 16 most sig- nificant bits of a 17-bit start address (i.e., word access). the screen 1 display start address is the memory address corresponding to the first displayed pixel (top left corner). in a dual panel configuration, screen 1 refers to the upper half of the display. while in a single panel configuration, screen 1 refers to the first screen of the split screen display feature where two differ- ent images (screen 1 and screen 2) can be displayed at the same time on one display. note the absolute address into display memory is determined by the memory mapping address which is set by vd13 - vd15 (see table 5-6, ?summary of power on / re- set options,? on page 26). aux[05] total display line count (msb) and wf count register i/o address = 0101b, read/write wf count bit 5 wf count bit 4 wf count bit 3 wf count bit 2 wf count bit 1 wf count bit 0 total disp. line count bit 9 total disp. line count bit 8 aux[06] screen 1 display start address register (lsb) i/o address = 0110b, read/write. screen 1 display start addr bit 7 screen 1 display start addr bit 6 screen 1 display start addr bit 5 screen 1 display start addr bit 4 screen 1 display start addr bit 3 screen 1 display start addr bit 2 screen 1 display start addr bit 1 screen 1 display start addr bit 0 aux[07] screen 1 display start address register (msb) i/o address = 0111b, read/write. screen 1 display start addr bit 15 screen 1 display start addr bit 14 screen 1 display start addr bit 13 screen 1 display start addr bit 12 screen 1 display start addr bit 11 screen 1 display start addr bit 10 screen 1 display start addr bit 9 screen 1 display start addr bit 8
epson research and development page 67 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 aux[08] bits 7-0 screen 2 display start address bits [15:0] aux[09] bits 7-0 these 16 bits determine the screen 2 display start address. in an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). in a 16-bit memory configuration these are the 16 most sig- nificant bits of a 17-bit start address (i.e., word access). in a dual panel configuration, screen 2 refers to the lower half of the display. the screen 2 display start address is the memory address corresponding to the first displayed pixel in the first line of the lower half of the display. if screen 2 is started right after screen 1, the screen 2 display start address can be calculated with the following formula: in a single panel configuration, screen 2 refers to the second screen of the split screen display feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. the screen 2 display start address is the memory address corresponding to the first pixel of the second image stored in display memory. to display screen 2 refer to aux[0a] screen 1 display line count register (lsb) on page 68. aux[08] screen 2 display start address register (lsb) i/o address = 1000b, read/write. screen 2 display start addr bit 7 screen 2 display start addr bit 6 screen 2 display start addr bit 5 screen 2 display start addr bit 4 screen 2 display start addr bit 3 screen 2 display start addr bit 2 screen 2 display start addr bit 1 screen 2 display start addr bit 0 aux[09] screen 2 display start address register (msb) i/o address = 1001b, read/write. screen 2 display start addr bit 15 screen 2 display start addr bit 14 screen 2 display start addr bit 13 screen 2 display start addr bit 12 screen 2 display start addr bit 11 screen 2 display start addr bit 10 screen 2 display start addr bit 9 screen 2 display start addr bit 8 screen 2 displaystartaddress hex () imagehorizontalresolution () imageverticalresolution () bytesperpixel () 2 memoryinterfacewidth 8 ---------------------------------------------------------------- ?? ?? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- screen 1 displaystartaddress + =
page 68 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 aux[0a] bits 7-0 screen 1 display line count bits [9:0] aux[0b] bits 1-0 these bits are the eight lsb of a 10-bit value used to determine the number of lines displayed for screen 1. the remaining lines will automatically display from the screen 2 display start address. the 10-bit value programmed is the number of display lines -1. this register is used to enable the split screen display feature (single panel only) where two different images can be displayed at the same time on one display. for example; aux[0a] = 20h for a 320x240 display system. the display will display 20h+1 = 33 lines on the upper part of the screen as dictated by the screen 1 display start address registers (aux[06] and aux[07]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the screen 2 display start address registers (aux[08] and aux[09]). two different images can be displayed when using a dual panel configuration by changing the screen 2 dis- play start address. however, by using this method screen 2 is limited to the lower half of the display. this register is ignored in dual panel mode. aux[0a] screen 1 display line count register (lsb) i/o address = 1010b, read/write. screen 1 display line count bit 7 screen 1 display line count bit 6 screen 1 display line count bit 5 screen 1 display line count bit 4 screen 1 display line count bit 3 screen 1 display line count bit 2 screen 1 display line count bit 1 screen 1 display line count bit 0 aux[0b] screen 1 display line count register (msb) i/o address = 1011b, read/write. n/a n/a n/a n/a n/a n/a screen 1 display line count bit 9 screen 1 display line count bit 8
epson research and development page 69 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 bits 7-0 horizontal non-display period bits [7:0] these bits are used to adjust the horizontal non-display period (see ?frame rate calculation? on page 84 for details). when these bits = 0, the fixed default non-display period (dhndp) is used. otherwise, a non-display period of dhndp & aux[0c] +1 is used. the unit of aux[0c] is the same as the unit of line byte count register, i.e. number of bytes to be fetched. see description of aux[02] and section 9.3 on page 84 for details. for example, if an additional 32 pixels wide of horizontal non-display period is desired in a 4 grays (2 bits-per-pixel) and 16-bit display memory interface system: aux[0c] = [32 / (16 / 2)] - 1 = 3. note that the value programmed determines the period of one line, and hence affects the frame period. bits 7-0 address pitch adjustment bits [7:0] this register controls the virtual display by setting the numerical difference between the last address of a display line, and the first address in the following line. if the address pitch adjustment is not equal to zero, then a virtual screen is formed. the size of the virtual screen is only limited by the available display memory. the actual display output is a window that is part of the whole image stored in the display memory. for example, with 128k of display memory, a 640x400 16-gray image can be stored. if the output display size is 320x240, then the whole image can be seen by changing display starting addresses through aux[06] and [07], and aux[08] and [09]. note that a virtual screen can be produced on either a single or dual panel. in 8-bit memory interface, if the address pitch adjustment is not equal to zero, a virtual screen with a line length of (line byte count +aux[0d]) bytes is created, with the display reflecting the contents of a win- dow (line byte count+1) bytes wide. the position of the window on the virtual screen is determined by aux[06] and [07], and aux[08] and [09]. in 16-bit memory interface, if the address pitch adjustment is not equal to zero, then a virtual screen with a line length of 2x(line byte count +aux[0d]) bytes is created, with the display reflecting the contents of a window 2x(line byte count+1) bytes wide. the position of the window on the virtual screen is deter- mined by aux[06] and [07], and aux[08] and [09]. aux[0c] horizontal non-display period i/o address = 1100b, read/write. horizontal non- display period bit 7 horizontal non- display period bit 6 horizontal non- display period bit 5 horizontal non- display period bit 4 horizontal non- display period bit 3 horizontal non- display period bit 2 horizontal non- display period bit 1 horizontal non- display period bit 0 aux[0d] address pitch adjustment register i/o address = 1101b, read/write. addr pitch adjustment bit 7 addr pitch adjustment bit 6 addr pitch adjustment bit 5 addr pitch adjustment bit 4 addr pitch adjustment bit 3 addr pitch adjustment bit 2 addr pitch adjustment bit 1 addr pitch adjustment bit 0
page 70 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 . the s1d13503 has three internal 16 position, 4-bit wide look-up tables (palettes). the 4-bit value programmed into each table position determines the output gray shade / color weighting of display data. these tables are bypassed in black-and- white (bw) display mode. these three 16 position look-up tables can be arranged in many different configurations to accommodate all the gray shade / color display modes. refer to look-up table architecture on page 72 for formats. bits 7-6 green bank bits [1:0] in 4-level gray / color display modes (2-bits/pixel), the 16 position green palette is arranged into four, 4 position ?banks?. these two bits control which bank is currently selected. these bits have no effect in 16- level gray / color display modes (4-bits/pixel). in 256 color display modes (8-bit/pixel), the 16 position green palette is arranged into two, 8 position ?banks? for the display of ?green? colors. only bit 0 of these two bits controls which bank is currently selected. bits 5-4 id bit / rgb index bits [1:0] these bits have dual purpose; id bits: after power on or hardware reset, these bits can be read to identify the s1d13503. these same bits are used to identify the pin compatible s1d13502 and would only be used in system implementations where common software is being used. as these bits are r/w they must be read before being written in order to be used as id bits. rgb index bits [1:0]: these bits are also used to provide access to the three internal look-up tables (rgb). aux[0e] look-up table address register i/o address = 1110b, read/write green bank bit 1 green bank bit 0 id bit / rgb index bit 1 id bit / rgb index bit 0 palette address bit 3 palette address bit 2 palette address bit 1 palette address bit 0 table 8-6: id bit usage chip aux[0e] bit 5 bit 4 power on or reset s1d13503 0 0 f352 0 1 s1d13502 1 0 s1d13502 1 1 table 8-7: look-up table access aux[0e] look-up table access bit 5 bit 4 0 0 auto-increment (see note 1) 0 1 red palette r/w access 1 0 green palette r/w access 1 1 blue palette r/w access
epson research and development page 71 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 note when auto-increment is selected, an internal pointer will default to the red palette on power on reset. each read/write access to aux[0f] will increment the counter to point to the next palette in order (rgb). whenever the look-up table address register aux[0e] is written, the rgb index will reset the pointer to the red palette. this pro- vides a efficient method for sequential writing of rgb data. bits 3-0 palette address bits [3:0] these 4 bits provide a pointer into the 16 position look-up table currently selected for cpu r/w access. note the look-up table configuration (e.g. 1/2/4 banks) does not affect the r/w access from the cpu as all 16 positions can be accessed sequentially. bit 7-6 red bank bits [1:0] in 4-level color display modes, the 16 position red palette is arranged into four, 4 position ?banks?. these two bits control which bank is currently selected. in 256 color display modes, the 16 position, red palette is arranged into two, 8 position ?banks? for the display of ?red? colors. only bit 0 of these two bits controls which bank is currently selected. these bits have no effect in all gray shade or 16-color display modes. bit 5-4 blue bank bits [1:0] in both the 4 and 256 color display modes, the 16 position blue palette is arranged into four 4 position ?banks? for the display of ?blue? colors. these two bits control which bank is currently selected. these bits have no effect in all gray shade display modes or 16 color display modes. bits 3-0 palette data bits [3:0] these 4-bits are the gray shade / color values used for display data output. they are programmed into the 4-bit look-up table (palettes) positions pointed to by palette address bits [3:0] and rgb index bit[1:0] (if in color display modes). for example; in a 16-level gray shade display mode, a data value of 0001b (4-bits / pixel) will point to look-up table position one and display the 4-bit gray shade corresponding to the value programmed into that location. aux[0f] look-up table data register i/o address = 1111b, read/write. red bank bit 1 red bank bit 0 blue bank bit 1 blue bank bit 0 palette data bit 3 palette data bit 2 palette data bit 1 palette data bit 0
page 72 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 8.2 look-up table architecture 8.2.1 gray shade display modes 4-level gray shade mode figure 37: 4-level gray-shade mode look-up table architecture table 8-8: look-up table configurations display mode 4-bit wide palette red green blue black & white 4-level gray 4 banks of 4 16-level gray 1 bank of 16 4 color 4 banks of 4 4 banks of 4 4 banks of 4 16 color 1 bank of 16 1 bank of 16 1 bank of 16 256 color 2 banks of 8 2 banks of 8 4 banks of 4 indicates the palette is not used for that display mode green look-up table 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 bank select bits [1:0] (aux[0e] bits [7:6]) 4-bit display data output bank select logic note: the above depiction is intended to show the display data output path only. the cpu r/w access to the individual look-up tables is not affected by the various ?banking? configurations.
epson research and development page 73 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 16-level gray shade mode figure 38: 16-level gray-shade mode look-up table architecture note the look-up table is bypassed in black-and-white display mode 4-bit pixel data ( p3, p2, p1, p0 ) 4-bit look-up table data output msb lsb green look-up table 16x4 0 1 2 3 c d e f
page 74 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 8.2.2 color display modes 4-level color mode figure 39: 4-level color mode look-up table architecture 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 red bank select bits [1:0] (aux[0f] bits [7:6]) bank select logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 green bank select bits [1:0] (aux[0e] bits [7:6]) bank select logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 blue bank select bits [1:0] (aux[0f] bits [5:4]) bank select logic red look-up table green look-up table blue look-up table 4-bit ?green? 4-bit ?red? display data output display data output 4-bit ?blue? display data output
epson research and development page 75 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 16-level color mode figure 40: 16-level color mode look-up table architecture 4-bit pixel data 4-bit ?red? look-up table data output red look-up table 16x4 0 1 2 3 c d e f 4-bit ?green? look-up table data output green look-up table 16x4 0 1 2 3 c d e f 4-bit ?blue? look-up table data output blue look-up table 16x4 0 1 2 3 c d e f
page 76 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 256-level color mode figure 41: 256-level color mode look-up table architecture red look-up table 0 1 2 3 4 5 6 7 bank 0 0 1 2 3 4 5 6 7 bank 1 bank select logic 3-bit pixel data 0 1 2 3 4 5 6 7 bank 0 0 1 2 3 4 5 6 7 bank 1 bank select logic 3-bit pixel data 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 blue bank select bits [1:0] (aux[0f] bits [5:4]) bank select logic blue look-up table green look-up table green bank select bit (aux[0e] bit 6) red bank select bit (aux[0f] bit 6) 76543210 r 2 r 1 r 0 g 2 g 1 g 0 b 1 b 0 256 color data format: 4-bit ?green? 4-bit ?red? display data output display data output 4-bit ?blue? display data output (r2, r1, r0) (g2, g1, g0) (b1, b0)
epson research and development page 77 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 8.3 power save modes two software-controlled power save modes have been incorporated into the s1d13503 to accommodate the important need for power reduction in the hand-held devices market. these modes can be enabled by setting the two power save bits (aux[03] bits 7:6). the various settings are: 8.3.1 power save mode 1 power save mode 1 has two states. initially when set, the s1d13503 enters state 1. if no valid memory cycle is detected within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter state 2. the number of clocks of inactivity before entering state 2 is dependent on the display memory interface and the number of gray shades. state 1 i/o read/write of all registers allowed memory read/write allowed lcd outputs are either forced low (aux[03] bit 5=0), or high impedance (aux[03] bit 5=1) state 2 the same as state 1 as well as: master clock for display memory access is disabled once a valid memory read/write cycle is detected, the s1d13503 returns to state 1 where the mpu access is serviced. the transition from going from state 2 to state 1 requires 1, 2, or 4 clocks (as described above). 8.3.2 power save mode 2 i/o read/write of all registers allowed memory read/write is disabled master clock for display memory access is disabled lcd outputs are either forced low (aux[03] bit 5=0), or high impedance (aux[03] bit 5=1) internal oscillator is disabled. table 8-9: power save mode selection bit 5 bit 4 mode activated 0 0 normal operation 0 1 power save mode 1 1 0 power save mode 2 11 reserved
page 78 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 8.3.3 power save mode function summary 8.3.4 pin states in power save modes note 1. internal register aux[03], bit 5 = 1 2. internal register aux[03], bit 5 = 0 table 8-10: power save mode function summary function power save mode (psm) normal (active) psm1 psm2 state 1 state 2 display active? yes no no no i/o access possible? yes yes yes yes memory access possible? yes yes no no sequence controller running? yes no no no internal oscillator disabled? no no no yes table 8-11: pin states in power save modes pin pin state normal (active) psm1 psm2 state 1 state 2 ud[3:0], ld[3:0], lp, xscl, yd, wf/xscl2 (note 1) active high impedance high impedance high impedance ud[3:0], ld[3:0], lp, xscl, yd, wf/xscl2 (note 2) active forced low forced low forced low ab[19:0], db[15:0] active active active active ior#, iow# active active active active memr#, memw# active active active active reset active active active active
epson research and development page 79 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 9 display memory interface 9.1 sram configurations supported 9.1.1 8-bit mode figure 42: 8-bit mode - 8k bytes sram figure 43: 8-bit mode - 16k bytes sram (requires aux[01] bit 0 = 0) 8kx8 s1d13503 vwe# vd0-7 vcs0# vcs1# va 0 - 1 2 we# cs# n/c 8kx8 s1d13503 vwe# vd0-7 vcs0# vcs1# va 0 - 1 2 we# cs# 8kx8 we# cs#
page 80 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 44: 8-bit mode - 32k bytes sram (requires aux[01] bit 0 = 1) figure 45: 8-bit mode - 40k bytes sram [either (8kx8 + 32kx8) requiring aux[01] bit 0 = 0 or (32kx8 + 8kx8) requiring aux[01] bit 0 = 1] 32kx8 s1d13503 vwe# vd0-7 vcs0# vcs1# va 0 - 1 4 we# cs# n/c 8k/32kx8 s1d13503 vwe# vd0-7 vcs0# vcs1# va 0 - 1 4 we# cs# 32k/8kx8 we# cs#
epson research and development page 81 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 figure 46: 8-bit mode - 64k bytes sram (requires aux[01] bit 0 = 1) 9.1.2 16-bit mode figure 47: 16-bit mode - 16k bytes sram 32kx8 s1d13503 vwe# vd0-7 vcs0# vcs1# va 0 - 1 4 we# cs# 32kx8 we# cs# s1d13503 vwe# vd0-7 vd8-15 vcs0# vcs1# va 0 - 1 2 8kx8 we# cs# 8kx8 cs# we#
page 82 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 48: 16-bit mode - 64k bytes sram figure 49: 16-bit mode - 128k bytes sram s1d13503 vwe# vd0-7 vd8-15 vcs0# vcs1# va 0 - 1 4 32kx8 we# cs# 32kx8 cs# we# s1d13503 vwe# vd0-7 vd8-15 vcs0# vcs1# va0-15 we# ub# lb# a0-15 i/o 1-8 i/o 9-16
epson research and development page 83 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 9.2 sram access time 9.2.1 8-bit display memory interface: 9.2.2 16-bit display memory interface: table 9-1: 8-bit display memory interface sram access time display mode 3v/3.3v 5v 16-level gray shades / 16-level colors access time < 1 / f osc - 40ns access time < 1 / f osc - 25ns 4-level gray shades / 4-level colors access time < 2 / f osc - 40ns access time < 2 / f osc - 25ns black-and-white (bw) access time < 2 / f osc - 40ns access time < 2 / f osc - 25ns table 9-2: 16-bit display memory interface sram access time display mode 3v/3.3v 5v 256-level colors access time < 1 / f osc - 40ns access time < 1 / f osc - 25ns 16-level gray shades / 16-level colors access time < 2 / f osc - 40ns access time < 2 / f osc - 25ns 4-level gray shades / 4-level colors access time < 4 / f osc - 40ns access time < 4 / f osc - 25ns black-and-white (bw) access time < 4 / f osc - 40ns access time < 4 / f osc - 25ns
page 84 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 9.3 frame rate calculation 9.3.1 for single panel black-and-white (bw) display mode: all other display modes: 9.3.2 for dual panel black-and-white (bw) display mode: all other display modes: where dhndp is default horizontal non-display period in term of pixels : dhndp = 16 pixels per panel in gray shade display modes, and dhndp = 32 pixels per panel in bw display mode and in color display modes. where phndp is programmable horizontal non-display period in term of pixels : phndp = 0 pixels when aux[0c] = 0, and phndp = pixels when aux[0c] not equal to zero. framerate 2 f osc horizontalpixels phndp dhndp ++ () verticallines 4 + () ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------ - = framerate f osc horizontalpixels phndp dhndp ++ () verticallines 4 + () ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------ - = framerate 2 f osc horizontalpixels phndp dhndp ++ () 2 verticallines 2 ------------------------------------ 2 + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------- = framerate f osc horizontalpixels phndp dhndp ++ () 2 verticallines 2 ------------------------------------ 2 + ?? ?? ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------- = aux 0 c [] 1 + () memoryinterfacewidth () bitsperpixel () ---------------------------------------------------------------------------------------------------------------- -
epson research and development page 85 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 9.4 memory size calculation memory size (bytes) = example : for a 640x480, 4 gray shades (2 bits-per-pixel) system : memory size (bytes) = 9.5 memory size requirement the following tables summarize the preceding information (formulae). input clock (f osc ) is limited by sram access time depending on the display mode and display memory interface that is being used. as a result, different resolutions will have different input clock and memory requirements for a particular frame rate. tables 9-3 through 9-5 summarize the minimum memory size and access time requirements for various resolutions at a particular input clock along with the corresponding frame rates. (1) memory more than 128kb cannot be supported by s1d13503. (2) memory more than 64kb can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface. * kb = k byte = 1024 bytes table 9-3: memory size requirement: number of horizontal pixels = 640 number of horizontal pixels = 640 display mode black-and-white (bw) (1 bit-per-pixel) 4 grays / 4 colors (2 bits-per-pixel) 16 grays / 16 colors (4 bits-per-pixel) 256 colors (8 bits-per-pixel) condition aux[0c] = aux[02] aux[0c] = 0 aux[0c] = 0 aux[0c] = 0 example display memory interface size access time size access time size access time size access time input clock (f osc ) frame rate (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v bw / gray color 480 8-bit 16-bit 37.5 40 ns 125 ns 55 ns 140 ns 75 (2) 125 ns (2) 140 ns 150 (1) (1) 300 (1) (1) 24 mhz 76 hz 74 hz 400 8-bit 16-bit 32 60 ns 160 ns 75 ns 175 ns 62.5 60 ns 160 ns 75 ns 175 ns 125 (2) 60 ns (2) 75 ns 250 (1) (1) 20 mhz 75 hz 74 hz 320 8-bit 16-bit 25 85 ns 210 ns 100 ns 225 ns 50 85 ns 210 ns 100 ns 225 ns 100 (2) 85 ns (2) 100 ns 200 (1) (1) 16 mhz 75 hz 73 hz 256 8-bit 16-bit 20 125 ns 290 ns 140 ns 305 ns 40 125 ns 290 ns 140 ns 305 ns 80 (2) 125 ns (2) 140 ns 160 (1) (1) 12 mhz 70 hz 69 hz 240 8-bit 16-bit 19 125 ns 290 ns 140 ns 305 ns 37.5 125 ns 290 ns 140 ns 305 ns 75 (2) 125 ns (2) 140 ns 150 (1) (1) 12 mhz 75 hz 73 hz 200 8-bit 16-bit 16 160 ns 360 ns 175 ns 375 ns 32 160 ns 360 ns 175 ns 375 ns 62.5 60 ns 160 ns 75 ns 175 ns 125 (2)(3) 60 ns (2)(3) 75 ns 10 mhz 75 hz 73 hz horizontalpixels () verticallines () bitsperpixel () 8 ------------------------------------------------------------------------------------------------------------------------------- ---------------- - 640 () 480 () 2 () 8 ----------------------------------------------- - 76800 bytes 75 kbyte == number of vertical lines
page 86 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 table 9-4: memory size requirement: number of horizontal pixels = 480 table 9-5: memory size requirement: number of horizontal pixels = 320 (1) memory more than 128kb cannot be supported by s1d13503. (2) memory more than 64kb can only be supported through 16-bit display memory interface. (3) 256 color mode must use 16-bit display memory interface. * kb = k byte = 1024 bytes number of horizontal pixels = 480 display mode black-and-white (bw) (1 bit-per-pixel) 4 grays / 4 colors (2 bits-per-pixel) 16 grays / 16 colors (4 bits-per-pixel) 256 colors (8 bits-per-pixel) condition aux[0c] = aux[02] aux[0c] = 0 aux[0c] = 0 aux[0c] = 0 example display memory interface size access time size access time size access time size access time input clock (f osc ) frame rate (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v bw / gray color 480 8-bit 16-bit 29 70 ns 180 ns 85 ns 195 ns 57 70 ns 180 ns 85 ns 195 ns 113 (2) 70 ns (2) 85 ns 225 (1) (1) 18 mhz 75 hz 73 hz 400 8-bit 16-bit 23.5 100 ns 240 ns 115 ns 255 ns 47 100 ns 240 ns 115 ns 255 ns 94 (2) 100 ns (2) 115 ns 188 (1) (1) 14 mhz 70 hz 68 hz 320 8-bit 16-bit 19 125 ns 290 ns 140 ns 305 ns 37.5 125 ns 290 ns 140 ns 305 ns 75 (2) 125 ns (2) 140 ns 150 (1) (1) 12 mhz 75 hz 72 hz 256 8-bit 16-bit 15 160 ns 360 ns 175 ns 375 ns 30 160 ns 360 ns 175 ns 375 ns 60 60 ns 160 ns 75 ns 175 ns 120 (2)(3) 60 ns (2)(3) 75 ns 10 mhz 77 hz 75 hz 240 8-bit 16-bit 14.5 210 ns 460 ns 225 ns 475 ns 29 210 ns 460 ns 225 ns 475 ns 57 85 ns 210 ns 100 ns 225 ns 113 (2)(3) 85 ns (2)(3) 100 ns 8 mhz 66 hz 64 hz 200 8-bit 16-bit 12 210 ns 460 ns 225 ns 475 ns 23.5 210 ns 460 ns 225 ns 475 ns 47 85 ns 210 ns 100 ns 225 ns 94 (2)(3) 85 ns (2)(3) 100 ns 8 mhz 79 hz 77 hz number of horizontal pixels = 320 display mode black-and-white (bw) (1 bit-per-pixel) 4 grays / 4 colors (2 bits-per-pixel) 16 grays / 16 colors (4 bits-per-pixel) 256 colors (8 bits-per-pixel) condition aux[0c] = aux[02] aux[0c] = 0 aux[0c] = 0 aux[0c] = 0 example display memory interface size access time size access time size access time size access time input clock (f osc ) frame rate (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v (kb) 3v/3.3v 5v bw / gray color 480 8-bit 16-bit 19 125 ns 290 ns 140 ns 305 ns 37.5 125 ns 290 ns 140 ns 305 ns 75 (2) 125 ns (2) 140 ns 150 (1) (1) 12 mhz 74 hz 70 hz 400 8-bit 16-bit 16 160 ns 360 ns 175 ns 375 ns 32 160 ns 360 ns 175 ns 375 ns 62.5 60 ns 160 ns 75 ns 175 ns 125 (2)(3) 60 ns (2)(3) 75 ns 10 mhz 74 hz 70 hz 320 8-bit 16-bit 12.5 210 ns 460 ns 225 ns 475 ns 25 210 ns 460 ns 225 ns 475 ns 50 85 ns 210 ns 100 ns 225 ns 100 (2)(3) 85 ns (2)(3) 100 ns 8 mhz 73 hz 70 hz 256 8-bit 16-bit 10 290 ns 625 ns 305 ns 640 ns 20 290 ns 625 ns 305 ns 635 ns 40 125 ns 290 ns 140 ns 305 ns 80 (2)(3) 125 ns (2)(3) 140 ns 6 mhz 69 hz 66 hz 240 8-bit 16-bit 9.5 290 ns 625 ns 305 ns 640 ns 19 290 ns 625 ns 305 ns 640 ns 37.5 125 ns 290 ns 140 ns 305 ns 75 (2)(3) 125 ns (2)(3) 140 ns 6 mhz 73 hz 70 hz 200 8-bit 16-bit 8 360 ns 760 ns 375 ns 775 ns 16 360 ns 760 ns 375 ns 775 ns 32 160 ns 360 ns 175 ns 375 ns 62.5 (2)(3) 160 ns (2)(3) 175 ns 5 mhz 73 hz 70 hz number of vertical lines number of vertical lines
epson research and development page 87 vancouver design center hardware functional specification s1d13503 issue date: 01/01/29 x18a-a-001-08 10 mechanical data figure 50: mechanical drawing qfp5-100-s2 (s1d13503f00a) 0.65 0.1 0.30 0.1 1.6 0.8 0.1 23.2 0.04 20.0 0.1 14.0 0.1 17.2 0.04 0~12 0.15 0.05 2.7 0.1 index 100 130 31 50 51 80 81 qfp5-100pin-s2 (s1d13503) all dimensions in mm
page 88 epson research and development vancouver design center s1d13503 hardware functional specification x18a-a-001-08 issue date: 01/01/29 figure 51: mechanical drawing qfp15-100-std (s1d13503f01a) qfp15-100pin-std 125 75 51 50 26 76 100 index 0~12 14.0 0.1 14.0 0.1 16.0 0.4 16.0 0.4 0.168 0.1 0.5 1.4 0.1 0.125 0.1 0.5 0.2 (s1d13503) 1 all dimensions in mm
s1d13503 dot matrix graphics lcd controller programming notes and examples document number: x18a-g-002-06 copyright ? 1996, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 initializing the s1d13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 gray shades / colors and look-up tables . . . . . . . . . . . . . . . 18 3.1 pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 memory organization for one bit pixel (black-and-white) . . . . . . . . . . . . . . . 18 3.1.2 memory organization for two bit pixels (4 colors/gray shades) . . . . . . . . . . . . 18 3.1.3 memory organization for four bit pixels (16 colors/gray shades) . . . . . . . . . . . 19 3.1.4 memory organization for eight bit pixels (256 colors) . . . . . . . . . . . . . . . . . 19 3.2 look-up table (lut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.1 lut registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.2 look-up table description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.3 black-and-white (one bit/pixel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 3.2.4 four gray shades (two bits/pixel in monochrome mode) . . . . . . . . . . . . . . . . 26 3.2.5 four colors (two bits/pixel in color mode) . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.6 sixteen gray shades (four bits/pixel in monochrome mode) . . . . . . . . . . . . . . 30 3.2.7 sixteen colors (four bits/pixel in color mode) . . . . . . . . . . . . . . . . . . . . . 31 3.2.8 256 colors (eight bits/pixel in color mode) . . . . . . . . . . . . . . . . . . . . . . . 32 4 display memory models . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.1 s5u13503b00c evaluation board display memory . . . . . . . . . . . . . . . . . . . 36 4.2.2 display start address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3 common display memory requirements for lcd panel sizes: . . . . . . . . . . . . . 38 5 advanced techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 virtual displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 bitmaps and text displays . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 mapping of registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.1 indexed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.2 direct mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4 split screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.2 single panel lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4.3 dual panel lcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 panning and scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5.2 panning right and left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5.3 scrolling up and down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
page 4 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 5.6 power saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.6.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.6.2 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 identifying the s1d13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7 programming the s1d13503 . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.1 main loop code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.2 initialization code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.3 advanced functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
epson research and development page 5 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 list of tables table 3-1: number of bits as related to colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 3-2: id bit usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 3-3: look-up table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 3-4: look-up table configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 3-5: s1d13503 color look-up table for 256 color mode. . . . . . . . . . . . . . . . . . . . . . .2 3 table 3-6: s1d13503 black-to-white look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 3-7: s1d13503 inverted look-up table (white-to-black) . . . . . . . . . . . . . . . . . . . . . .2 5 table 3-8: s1d13503 black-to-white look-up table for 4 gray shades . . . . . . . . . . . . . . . . . .26 table 3-9: s1d13503 low to high intensity color look-up table for 4 colors . . . . . . . . . . . . . .28 table 3-10: simulation of first 16 entries of standard vga palette . . . . . . . . . . . . . . . . . . . . . 31 table 3-11: examples of 256 pixel colors using linear lut . . . . . . . . . . . . . . . . . . . . . . . . .32 table 4-1: memory size requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 5-1: smallest number of pixels for panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 5-2: power save mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 5-3: power save mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 5-4: power save mode function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 6-1: id bit usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
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epson research and development page 7 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 list of figures figure 1: pixel storage for 1 bit (black-and-white) in one byte of display memory . . . . . . . . . . 18 figure 2: pixel storage for 2 bits (4 colors/gray shades) in one byte of display memory . . . . . . . 18 figure 3: pixel storage for 4 bits (16 colors/gray shades) in one byte of display memory . . . . . . . 19 figure 4: pixel storage for 8 bits (256 colors) in one byte of display memory . . . . . . . . . . . . . 19 figure 5: 4-level gray-shade mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . 27 figure 6: 4-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7: 16-level gray-shade mode look-up table architecture . . . . . . . . . . . . . . . . . . . . 30 figure 8: 16-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 9: 256-level color mode look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10: memory map example for 320 x 240 lcd panel with 4 colors/gray shades . . . . . . . . . 38 figure 11: memory map example for 320 x 240 lcd panel with 256 colors . . . . . . . . . . . . . . . 39 figure 12: memory map example for 640 x 200 lcd panel with 16 colors/gray shades . . . . . . . . . 39 figure 13: moving a viewport inside a virtual display . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14: font for the message ?text? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15: display memory contents for message ?text? in 256 color mode . . . . . . . . . . . . . . . 43 figure 16: memory map for split screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17: 320 x 240 single panel for split screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 18: 640 x 480 dual panel for split screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 19: memory map for a dual panel showing a single image . . . . . . . . . . . . . . . . . . . . 51 figure 20: display for 13503demo.exe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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epson research and development page 9 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 1 introduction the purpose of this guide is to demonstrate how to program the s1d13503 lcd controller, with reference made to the s5u13503b00c evaluation board. the first half of this guide presents the basic concepts of lcd controllers. the second half of this guide presents programming examples which are combined in a simple menu-driven program. most of the program is written in the ?c? programming language, with some parts written in 8086 assembly.
page 10 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 2 initializing the s1d13503 this section presents two examples to show how to initialize the s1d13503 registers and write a pixel to the display. code to initialize the s1d13503 is provided in section 7.2, ?initialization code? on page 60. the following examples describe values written to registers. a ?panel specific? value is one required for the given type of panel. such a value must never change after initializa- tion of all registers. an ?implementation specific? value is one required for the hardware implementation of the s1d13503. such a value must never change after initialization of all registers. refer to the s1d13503 hardware functional specification and s5u13503b00c evaluation board user?s manual for more information on hardware implementation issues. an ?application specific? value is one that can be changed by the program after initialization of all registers. example 1: initialize the registers for a 256 color 320 x 240 single panel lcd with 128k of display memory. afterwards write one pixel to the top left corner of the display. program s1d13503 registers in the following order with the data supplied: aux register data (in binary) notes see also aux[00h] 0000 0000 bits 7 and 6 must be zero aux[01h] 0010 1001 b7 = display off (application specific; the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on) b6 = single panel (panel specific) b5 = xscl is masked (panel specific) b4 = lcde = lcdenb pin = set to disable specific power supply design (for s5u13503b00c, set bit to 0 to disable power supply) (application specific; the recommended procedure is to disable the power supply during register initialization and afterwards enable the power supply) b3 = n/a for 256 colors (application specific) b2 = 4 bit lcd data width when combined with aux[03] bit 3 (panel specific) b1 = 16 bit memory interface (implementation specific) b0 = rams ignored (implementation specific) aux[02h] 1001 1111 bits 7-0 = bits 7-0 of line byte count bit 8 of line byte count is bit 0 of aux[03h] see note a at end of table for calculation aux[03h] 0000 0110 bits 7-6 = power save mode 0 (application specific - for normal operation set to 00b) bit 5 = lcd interface signals forced low during power save (implementation and panel specific) bit 4 = no lut bypass (application specific) bit 3 = 4 bit lcd data width when combined with aux[01] bit 2 (panel specific) bit 2 = 256 color mode (application specific) bit 1 = color panel attached (panel specific) bit 0 = bit 8 of line byte count (panel specific, see aux[02h]) see section 5.6, ?power saving? on page 54 aux[04h] 1110 1111 bits 7-0 = bits 7-0 of total display line count bits 9-8 of total display line count in bits 1-0 of aux[05h] see note b and c at end of table for calculation
epson research and development page 11 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 aux[05h] 0000 0000 bits 7-2: 0 = wf output toggles every frame (panel specific) bits 1-0 = bits 9-8 of total display line count (panel specific, see aux[04h]) aux[06h] aux[07h] 0000 0000 0000 0000 bits 15-0 of screen 1 display start address - normally screen 1 start address = 0000h (application and panel specific) bits 7-0 are in aux[06h] and bits 15-8 are in aux[07h] when 0000h, screen 1 display start address is located at d000:0000h, bank 0, on the s5u13503b00c see section 4.2.1, ?s5u13503b00c evaluation board display memory? on page 36 and section 4.1, ?registers? on page 34 aux[08h] aux[09h] 0000 0000 0000 0000 bits 15-0 of screen 2 display start address - normally screen 2 start address = 0000h (application and panel specific) bits 7-0 are in aux[08h] and bits 15-8 are in aux[09h] when 0000h, screen 1 display start address is located at d000:0000h, bank 0, on the s5u13503b00c see section 4.2.1, ?s5u13503b00c evaluation board display memory? on page 36 and section 4.1, ?registers? on page 34 aux[0ah] 1110 1111 bits 7-0 = bits 7-0 of screen 1 display line count bits 9-8 of screen 1 display line count in bits 1-0 of aux[0bh] screen 1 display line count is typically the same as total display line count (aux[0ah] = aux[04h], bits 1-0 of aux[0bh] = bits 1-0 of aux[05h]) see section 5.4, ?split screen? on page 45 aux[0bh] 0000 0000 bits 7-2 = don?t care; recommend clearing bits bits 1-0 = bits 9-8 of screen 1 display line count (application specific, see aux[0ah]) aux[0ch] 0000 0000 normally programmed to 00h (panel specific) bits 7-0 = use fixed default non-display period aux[0dh] 0000 0000 normally programmed to 00h (normal) bits 7-0 = no address pitch adjustment when 0 see section 5.1, ?virtual displays? on page 40 aux[0eh] 0000 0000 select palette address bits 7-6 = green bank 0 (application specific) bits 5-4 = auto increment palette r/w access (application specific) bits 3-0 = palette address (application specific) aux[0fh] 0000 0000 write red data bits 7-6 = red bank 0 (application specific) bits 5-4 = blue bank 0 (application specific) bits 3-0 = palette data (application specific) aux[0fh] 0000 0000 write green data aux[0fh] 0000 0000 write blue data aux[0eh] 0000 0001 increment palette address aux[0fh] 0000 0010 write red data aux[0fh] 0000 0010 write green data aux[0fh] 0000 0101 write blue data aux[0eh] 0000 0010 increment palette address aux register data (in binary) notes see also
page 12 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 aux[0fh] 0000 0100 write red data aux[0fh] 0000 0100 write green data aux[0fh] 0000 1010 write blue data aux[0eh] 0000 0011 increment palette address aux[0fh] 0000 0110 write red data aux[0fh] 0000 0110 write green data aux[0fh] 0000 1111 write blue data aux[0eh] 0000 0100 increment palette address aux[0fh] 0000 1001 write red data aux[0fh] 0000 1001 write green data aux[0fh] 0000 1111 write blue data aux[0eh] 0000 0101 increment palette address aux[0fh] 0000 1011 write red data aux[0fh] 0000 1011 write green data aux[0fh] 0000 1010 write blue data aux[0eh] 0000 0110 increment palette address aux[0fh] 0000 1101 write red data aux[0fh] 0000 1101 write green data aux[0fh] 0000 0101 write blue data aux[0eh] 0000 0111 increment palette address aux[0fh] 0000 1111 write red data aux[0fh] 0000 1111 write green data aux[0fh] 0000 0000 write blue data aux[0eh] 0000 1000 increment palette address aux[0fh] 0000 1111 write red data aux[0fh] 0000 1111 write green data aux[0fh] 0000 0001 write blue data aux[0eh] 0000 1001 increment palette address aux[0fh] 0000 1101 write red data aux[0fh] 0000 1101 write green data aux[0fh] 0000 0110 write blue data aux[0eh] 0000 1010 increment palette address aux[0fh] 0000 1011 write red data aux[0fh] 0000 1011 write green data aux[0fh] 0000 1001 write blue data aux[0eh] 0000 1100 increment palette address aux[0fh] 0000 0110 write red data aux[0fh] 0000 0110 write green data aux register data (in binary) notes see also
epson research and development page 13 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 note a b single panel cdual panel aux[0fh] 0000 1101 write blue data aux[0eh] 0000 1101 increment palette address aux[0fh] 0000 0100 write red data aux[0fh] 0000 0100 write green data aux[0fh] 0000 1001 write blue data aux[0eh] 0000 1110 increment palette address aux[0fh] 0000 0010 write red data aux[0fh] 0000 0010 write green data aux[0fh] 0000 0100 write blue data aux[0eh] 0000 1111 select palette address aux[0fh] 0000 0000 write red data aux[0fh] 0000 0000 write green data aux[0fh] 0000 0010 write blue data aux[01h] 1011 1001 program mode register bit disp to 1, and set lcde to enable power supply 1001 0000b ?or? {original value for aux[01h]} b7 = display on (application specific) b4 = lcde = lcdenb pin = set to enable specific power supply design (for s5u13503b00c, set bit to 1 to enable power supply) (application specific) write one pixel to the top left corner of display memory. if the s5u13503b00c evaluation board is used in indexed i/o mode, there are two video memory banks which begin at d000:0000 (2 banks x 64k per bank; see the following note). if the base port address is 310h, then read from port address 312h. next, write 0ffh to location d000:0000h; this will be seen as a white pixel at the top left corner of the display. aux register data (in binary) notes see also line byte count bits per pixel memory interface width ----------------------------------------------------------- - horizontal resolution ?? ?? 1 ? = 8 16 ----- - 320 ?? ?? 1 ? 159 9fh === total display line count number of display lines 1 ?2401 ? 239 0efh ==== total display line count number of display lines 2 -------------------------------------------------------------- 1 ? =
page 14 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 note the s5u13503b00c evaluation board maps the 128k of display memory into two banks of 64k, start- ing at d000:0000. this permits a vga card to work along with the s1d13503b00c card. bank 0 repre- sents the first 64k of display memory, and is selected by reading from the base port address+2. bank 1 represents the second 64k of display memory, and is selected by writing to the base port address+2. the values read from or written to the base port address+2 are not important; only the action of reading or writing is significant. this method of memory banking will only work if the s5u13503b00c is set for indexed port i/o and is specific to this board. example 2: initialize the registers for a 4 gray shade 640 x 480 dual panel lcd with 128k of display memory. afterwards write one pixel to the top left corner of the display?s second panel. program s1d13503 registers in the following order with the data supplied: aux register data (in binary) notes see also aux[00h] 0000 0000 bits 7 and 6 must be zero aux[01h] 0100 0101 b7 = display off (application specific; the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on) b6 = dual panel (panel specific) b5 = xscl not masked (panel specific) b4 = lcde = lcdenb pin = set to disable specific power supply design (for s5u13503b00c, set bit to 0 to disable power supply) (application specific; the recommended procedure is to disable the power supply during register initialization and afterwards enable the power supply) b3 = 4 grays when combined with aux[03] bits 1 and 2 (application specific) b2 = 8 bit lcd data width (panel specific) b1 = 16 bit memory interface (implementation specific) b0 = rams ignored (implementation specific) aux[02h] 0100 1111 bits 7-0 = bits 7-0 of line byte count bit 8 of line byte count is bit 0 of aux[03h] see note a at end of table for calculation aux[03h] 0000 0000 bits 7-6 = power save mode 0 (application specific - for normal operation set to 00b) bit 5 = lcd interface signals forced low during power save (implementation and panel specific) bit 4 = no lut bypass (application specific) bit 3 = 4 bit lcd data width when combined with aux[01] bit 2 (panel specific) bit 2 = 4/16 gray shade mode (application specific) bit 1 = monochrome panel attached (panel specific) bit 0 = bit 8 of line byte count (panel specific, see aux[02h]) see section 5.6, ?power saving? on page 54 aux[04h] 1110 1111 bits 7-0 = bits 7-0 of total display line count bits 9-8 of total display line count in bits 1-0 of aux[05h] see note b and c at end of table for calculation aux[05h] 0000 0000 bits 7-2: 0 = wf output toggles every frame (panel specific) bits 1-0 = bits 9-8 of total display line count (panel specific, see aux[04h])
epson research and development page 15 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 aux[06h] aux[07h] 0000 0000 0000 0000 bits 15-0 of screen 1 display start address - normally screen 1 start address = 0000h (application and panel specific) bits 7-0 are in aux[06h] and bits 15-8 are in aux[07h] when 0000h, screen 1 display start address is located at d000:0000h, bank 0, on the s5u13503b00c see section 4.2.1, ?s5u13503b00c evaluation board display memory? on page 36 and section 4.1, ?registers? on page 34 aux[08h] aux[09h] 0000 0000 0100 1011 bits 15-0 of screen 2 display start address - normally screen 2 start address =4b00h (application and panel specific) bits 7-0 are in aux[08h] and bits 15-8 are in aux[09h] when 4b00h, screen 2 display start address is located at d000:9600h, bank 0, on the s5u13503b00c see section 4.2.1, ?s5u13503b00c evaluation board display memory? on page 36 and section 4.1, ?registers? on page 34 aux[0ah] 1110 1111 bits 7-0 = bits 7-0 of screen 1 display line count bits 9-8 of screen 1 display line count in bits 1-0 of aux[0bh] screen 1 display line count is typically the same as total display line count (aux[0ah] = aux[04h], bits 1-0 of aux[0bh] = bits 1-0 of aux[05h]) see section 5.4, ?split screen? on page 45 aux[0bh] 0000 0000 bits 7-2 = don?t care; recommend clearing bits bits 1-0 = bits 9-8 of screen 1 display line count (application specific, see aux[0ah]) aux[0ch] 0000 0000 normally programmed to 00h (panel specific) bits 7-0 = use fixed default non-display period aux[0dh] 0000 0000 normally programmed to 00h (normal) bits 7-0 = no address pitch adjustment when 0 see section 5.1, ?virtual displays? on page 40 aux[0eh] 0000 0000 select palette address bits 7-6 = green bank 0 (application specific) bits 5-4 = auto increment palette r/w access (application specific) bits 3-0 = palette address (application specific) aux[0fh] 0000 0000 write red data bits 7-6 = red bank 0 (application specific) bits 5-4 = blue bank 0 (application specific) bits 3-0 = palette data (application specific) aux[0fh] 0000 0000 write green data aux[0fh] 0000 0000 write blue data aux[0eh] 0000 0001 increment palette address aux[0fh] 0000 0010 write red data aux[0fh] 0000 0010 write green data aux[0fh] 0000 0101 write blue data aux[0eh] 0000 0010 increment palette address aux[0fh] 0000 0100 write red data aux[0fh] 0000 0100 write green data aux register data (in binary) notes see also
page 16 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 aux[0fh] 0000 1010 write blue data aux[0eh] 0000 0011 increment palette address aux[0fh] 0000 0110 write red data aux[0fh] 0000 0110 write green data aux[0fh] 0000 1111 write blue data aux[0eh] 0000 0100 increment palette address aux[0fh] 0000 1001 write red data aux[0fh] 0000 1001 write green data aux[0fh] 0000 1111 write blue data aux[0eh] 0000 0101 increment palette address aux[0fh] 0000 1011 write red data aux[0fh] 0000 1011 write green data aux[0fh] 0000 1010 write blue data aux[0eh] 0000 0110 increment palette address aux[0fh] 0000 1101 write red data aux[0fh] 0000 1101 write green data aux[0fh] 0000 0101 write blue data aux[0eh] 0000 0111 increment palette address aux[0fh] 0000 1111 write red data aux[0fh] 0000 1111 write green data aux[0fh] 0000 0000 write blue data aux[0eh] 0000 1000 increment palette address aux[0fh] 0000 1111 write red data aux[0fh] 0000 1111 write green data aux[0fh] 0000 0001 write blue data aux[0eh] 0000 1001 increment palette address aux[0fh] 0000 1101 write red data aux[0fh] 0000 1101 write green data aux[0fh] 0000 0110 write blue data aux[0eh] 0000 1010 increment palette address aux[0fh] 0000 1011 write red data aux[0fh] 0000 1011 write green data aux[0fh] 0000 1001 write blue data aux[0eh] 0000 1100 increment palette address aux[0fh] 0000 0110 write red data aux[0fh] 0000 0110 write green data aux[0fh] 0000 1101 write blue data aux[0eh] 0000 1101 increment palette address aux register data (in binary) notes see also
epson research and development page 17 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 note a. b single panel cdual panel aux[0fh] 0000 0100 write red data aux[0fh] 0000 0100 write green data aux[0fh] 0000 1001 write blue data aux[0eh] 0000 1110 increment palette address aux[0fh] 0000 0010 write red data aux[0fh] 0000 0010 write green data aux[0fh] 0000 0100 write blue data aux[0eh] 0000 1111 select palette address aux[0fh] 0000 0000 write red data aux[0fh] 0000 0000 write green data aux[0fh] 0000 0010 write blue data aux[01h] 1101 0101 program mode register bit disp to 1, and set lcde to enable power supply 1001 0000b ?or? {original value for aux[01h]} b7 = display on (application specific) b4 = lcde = lcdenb pin = set to enable specific power supply design (for s5u13503b00c, set bit to 1 to enable power supply) (application specific) write one pixel to the top left corner of the display?s second panel. if the s5u13503b00c evaluation board is used in indexed mode, there are two video memory banks which begin at d000:0000 (2 banks x 64k per bank; see the note on page 14). if the base port address is 310h, then read from port address 312h. next, write 0c0h to location d000:9600h; this will be seen as a white pixel at the top left corner of the display?s second panel. aux register data (in binary) notes see also line byte count bits per pixel memory interface width ----------------------------------------------------------- - horizontal resolution ?? ?? 1 ? = 2 16 ----- - 640 ?? ?? 1 ?794fh === total display line count number of display lines 1 ? = total display line count number of display lines 2 -------------------------------------------------------------- 1 ? 480 2 -------- -1 ? 239 0efh ====
page 18 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3 gray shades / colors and look-up tables this section discusses how the s1d13503 shows color and monochrome images on lcd panels. 3.1 pixels a pixel is physically stored in display memory as a series of bits. the more bits, the more colors the pixel can show. the following sections show how these pixels are stored in display memory. 3.1.1 memory organization for one bit pixel (black-and-white) to store one bit pixels, eight pixels are grouped into one byte of display memory as shown below: figure 1: pixel storage for 1 bit (black-and-white) in one byte of display memory when these pixels are shown, pixel 0 is seen to be left of pixel 1, pixel 1 is seen to be left of pixel 2, and so on. one bit pixels are only available on monochrome panels, and can only be displayed in black-and-white (no look-up table is used). 3.1.2 memory organization for two bit pixels (4 colors/gray shades) to store two bit pixels, four pixels are grouped into one byte of display memory as shown below: figure 2: pixel storage for 2 bits (4 colors/gray shades) in one byte of display memory when these pixels are shown, pixel 0 is seen to be left of pixel 1, pixel 1 is seen to be left of pixel 2, and so on. two bit pixels are available in both monochrome and color panels. table 3-1: number of bits as related to colors bits per pixel levels of gray shades colors 12 n/a 24 4 416 16 8n/a 256 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 bit 0 pixel 1 bit 0 pixel 2 bit 0 pixel 3 bit 0 pixel 4 bit 0 pixel 5 bit 0 pixel 6 bit 0 pixel 7 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 bit 1 pixel 0 bit 0 pixel 1 bit 1 pixel 1 bit 0 pixel 2 bit 1 pixel 2 bit 0 pixel 3 bit 1 pixel 3 bit 0
epson research and development page 19 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 3.1.3 memory organization for four bit pixels (16 colors/gray shades) to store four bit pixels, two pixels are grouped into one byte of display memory as shown below: figure 3: pixel storage for 4 bits (16 colors/gray shades) in one byte of display memory when these pixels are shown, pixel 0 is seen to be left of pixel 1. for color panels, each four bit pixel represents an index into the red, green, and blue luts. for monochrome panels, each four bit pixel represents an index into the green lut. 3.1.4 memory organization for eight bit pixels (256 colors) to store eight bit pixels, one pixel is stored in one byte of display memory as shown below: figure 4: pixel storage for 8 bits (256 colors) in one byte of display memory as shown above, the 256 color pixel is divided into three parts: three bits for red, three bits for green, and two bits for blu e. the red bits represent an index into the red lut, the green bits represent an index into the green lut, and the blue bits represent an index into the blue lut. eight bit pixels are only available in color panels. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pixel 0 bit 3 pixel 0 bit 2 pixel 0 bit 1 pixel 0 bit 0 pixel 1 bit 3 pixel 1 bit 2 pixel 1 bit 1 pixel 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 red bit 2 red bit 1 red bit 0 green bit 2 green bit 1 green bit 0 blue bit 1 blue bit 0
page 20 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2 look-up table (lut) this section provides a concise description of the lut registers, followed by a description of the color and monochrome luts. next is a series of examples which show how to initialize the luts, create an inverted lut, and how to select one of four banks in both the 4 gray shade and color modes. 3.2.1 lut registers the s1d13503 has three internal 16 position, 4-bit wide look-up tables (also referred to as palettes). the 4-bit value programmed into each table position determines the output gray shade / color weighting of display data. these tables are bypassed in black-and-white (bw) display mode. these three 16 position look-up tables can be arranged in many different configurations to accommodate all the gray shade / color display modes. refer to look-up table configurations on page 22 for formats. bits 7-6 green bank bits [1:0] in 4-level gray / color display modes (2-bits/pixel), the 16 position green palette is arranged into four, 4 position ?banks?. these two bits control which bank is currently selected. these bits have no effect in 16- level gray / color display modes (4-bits/pixel). in 256 color display modes (8-bit/pixel), the 16 position green palette is arranged into two, 8 position ?banks? for the display of ?green? colors. only bit 0 of these two bits controls which bank is currently selected. bits 5-4 id bit / rgb index bits [1:0] these bits have dual purpose; id bits: after ?power on? or hardware reset, these bits can be read to identify the current revision of the s1d13503. these same bits are used to identify the pin compatible s1d13502 and would only be used in system implementations where common software is being used. as these bits are r/w they must be read before being written in order to be used as id bits. aux[0e] look-up table address register i/o address = 1110b, read/write green bank bit 1 green bank bit 0 id bit / rgb index bit 1 id bit / rgb index bit 0 palette address bit 3 palette address bit 2 palette address bit 1 palette address bit 0 table 3-2: id bit usage chip aux[0e] bit 5 bit 4 power on or reset s1d13503 0 0 reserved 0 1 s1d13502 1 0 s1d13502 1 1
epson research and development page 21 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 rgb index bits [1:0]: these bits are also used to provide access to the three internal look-up tables (rgb). note when auto-increment is selected, an internal pointer will default to the red palette on power on reset. each read/write access to aux[0f] will increment the counter to point to the next palette in order (rgb). whenever the look-up table address register aux[0e} is written, the rgb index will reset the pointer to the red palette. this pro- vides a efficient method for sequential writing of rgb data. bits 3-0 palette address bits [3:0] these 4 bits provide a pointer into the 16 position look-up table currently selected for cpu r/w access. note the look-up table configuration (e.g. 1/2/4 banks) does not affect the r/w access from the cpu. all 16 positions can be accessed sequentially. bit 7-6 red bank bits [1:0] in 4-level color display modes, the 16 position red palette is arranged into four, 4 position ?banks?. these two bits control which bank is currently selected. in 256 color display modes, the 16 position, red palette is arranged into two, 8 position ?banks? for the display of ?red? colors. only bit 0 of these two bits controls which bank is currently selected. these bits have no effect in all gray shade or 16-color display modes. bit 5-4 blue bank bits [1:0] in both the 4 and 256 color display modes, the 16 position blue palette is arranged into four 4 position ?banks? for the display of ?blue? colors. these two bits control which bank is currently selected. these bits have no effect in all gray shade display modes or 16 color display modes. bits 3-0 palette data bits [3:0] these 4-bits are the gray shade / color values used for display data output. they are programmed into the 4-bit look-up table (palettes) positions pointed to by palette address bits [3:0] and rgb index bit[1:0] (if in color display modes). for example; in a 16-level gray shade display mode, a data value of 0001b (4-bits / pixel) will point to look-up table position one and display the 4-bit gray shade corresponding to the value programmed into that location. table 3-3: look-up table access aux[0e] look-up table access bit 5 bit 4 0 0 auto-increment (see note 1) 0 1 red palette r/w access 1 0 green palette r/w access 1 1 blue palette r/w access aux[0f] look-up table data register i/o address = 1111b, read/write. red bank bit 1 red bank bit 0 blue bank bit 1 blue bank bit 0 palette data bit 3 palette data bit 2 palette data bit 1 palette data bit 0
page 22 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2.2 look-up table description the look-up table (lut, or palette) treats the value of a pixel as an index into an array of colors or gray shades. for example, a pixel value of zero would point to the first lut entry; a pixel value of 7 would point to the eighth lut entry. the value inside each lut entry represents the intensity of the given color or gray shade. this value ranges between 0 and 0fh. the s1d13503 look-up table is linear; increasing the lut entry number results in a lighter color or gray shade. for example, a lut entry of 0fh into the red look-up entry will always result in a bright red output. an entry of 00h into a look-up entry will always result in the removal of this color (black if monochrome). because lut entries represent the actual colors shown on the lcd panel, pixel values indirectly select which color or gray shade to display. when the number of bits in a pixel is less than 4, there are several different lut configurations based on whether the display is monochrome or color, and the number of gray shades or colors. 3.2.2.1 color mode in color mode, the s1d13503 supports three 16 position, 4 bit wide color luts (red, green, and blue). depending on the selected pixel size, these luts will provide from 1 to 4 banks. 2 bits-per-pixel (4 colors) in this format the pixel is an index into the red, green, and blue luts. each color lut supports 4 banks (see section 3.2.5, ?four colors (two bits/pixel in color mode)? on page 28). 4 bits-per-pixel (16 colors) in this format the pixel is an index into the red, green, and blue luts. each color lut supports only one bank (see section 3.2.7, ?sixteen colors (four bits/pixel in color mode)? on page 31). 8 bits-per-pixel (256 colors) in this format the pixel is divided into three parts: 3 bits for red, 3 bits for green, and 2 bits for blue. if the red, green, and blue luts were programmed to show a linear increase in intensity of the given color, the 8 bit pixel describes the intensity of the given set of colors. for example, a pixel value of 00h would be black, e0h would be bright red, 1ch would be bright green, and 03h would be bright blue. because there are 16 entries for each color lut, the s1d13503 provides two red banks, two green banks, and four blue banks in 256 color mode (see section 3.2.8, ?256 colors (eight bits/pixel in color mode)? on page 32). table 3-4: look-up table configurations display mode 4-bit wide palette red green blue black & white 4-level gray 4 banks of 4 16-level gray 1 bank of 16 4 color 4 banks of 4 4 banks of 4 4 banks of 4 16 color 1 bank of 16 1 bank of 16 1 bank of 16 256 color 2 banks of 8 2 banks of 8 4 banks of 4 indicates the palette is not used for that display mode
epson research and development page 23 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 3.2.2.2 monochrome mode in monochrome mode, the s1d13503 treats the green lut as a 16 position, 4 bit wide monochrome lut. depending on the selected pixel size, this lut will provide from 1 to 4 banks. 1 bit-per-pixel (black-and-white) in this format no lut is used. a pixel value of 0 is black, and a pixel value of 1 is white. 2 bits-per-pixel (4 gray shades) in this format the pixel is an index into the monochrome lut. the monochrome lut supports 4 banks (see section 3.2.4, ?four gray shades (two bits/pixel in monochrome mode)? on page 26). 4 bits-per-pixel (16 gray shades) in this format the pixel is an index into the monochrome lut. the monochrome lut supports only one bank (see section 3.2.6, ?sixteen gray shades (four bits/pixel in monochrome mode)? on page 30). example 3: initialize the look-up table for 256 colors (bank 0 only) table 3-5 shows the color luts with intensities starting from black (index 0) and finishing in maximum color intensity (at the largest index available for the color in bank 0). for example, the red lut would have a maximum intensity at index 07h, the green lut would have a maximum intensity at index 07h, and the blue lut would have a maximum intensity at index 03h. a normal display would use bank 0 for the red, green, and blue luts. 1. write lut index to look-up table address register aux[0eh], set to automatic increment mode. 2. write red lut entry value to look-up table data register aux[0fh]. 3. write green lut entry value to look-up table data register aux[0fh]. 4. write blue lut entry value to look-up table data register aux[0fh]. 5. repeat steps 1-4 until all 16 lut entries have been written. table 3-5: s1d13503 color look-up table for 256 color mode index (hex) red lut (hex) green lut (hex) blue lut (hex) 00 0 0 12 2 5 24 4 a 36 6 f 49 9 x 5b b x 6d d x 7f f x where x is don?t care
page 24 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 example 4: initialize the look-up table for 16 gray shades the following describes how to initialize the look-up table for 16 gray shades. table 3-6 shows a lut with gray shades starting from black (index 0) and finishing in white (index 15, or 0fh). 1. write lut index to look-up table address register aux[0eh]. 2. write lut entry value to look-up table data register aux[0fh]. 3. repeat steps 1 and 2 until all 16 lut entries have been written. table 3-6: s1d13503 black-to-white look-up table index (hex) look-up ta b l e (hex) index (hex) look-up ta bl e (hex) 00 88 11 99 22 aa 33 bb 44 cc 55 dd 66 ee 77 ff
epson research and development page 25 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 example 5: initialize an inverted look-up table this example shows how to invert an image by changing only the lut. inverting means that pixels formally shown as light gray shades are now shown as dark gray shades, and vise versa. it does not matter whether the s1d13503 is in 4 gray shade or 16 gray shade mode. 1. read lut entry. write lut index to look-up table address register aux[0eh] read ?old lut entry? from look-up table data register aux[0fh] 2. calculate ?new lut entry? according to the following formula: 3. write lut entry back. write lut index to look-up table address register aux[0eh] write ?new lut entry? to look-up table data register aux[0fh] 4. repeat steps 1 to 3 until all 16 lut entries have been changed. if table 3-6 was previously programmed into the s1d13503, the new inverted lut would be the following: 3.2.3 black-and-white (one bit/pixel) when the s1d13503 is configured for one bit pixels, the monochrome (green) lut is not used. instead, a pixel value of 0 represents black and a pixel value of 1 represents white. note one bit/pixel is only available in monochrome mode. table 3-7: s1d13503 inverted look-up table (white-to-black) index (hex) look-up ta b l e (hex) index (hex) look-up ta bl e (hex) 0f 87 1e 96 2d a5 3c b4 4b c3 5a d2 69 e1 78 f0 new lut entry 15 old lut entry ? =
page 26 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2.4 four gray shades (two bits/pixel in monochrome mode) when the s1d13503 is configured for two bit pixels in monochrome mode, each pixel can index one of four monochrome lut entries. note that in monochrome mode, the s1d13503 uses the green lut as the monochrome lut. the 16 lut entries are divided into four separate look-up tables or banks , each having four entries (see figure 5). the following examples show how to program and select these banks. example 6: in 4 gray shade mode, program bank 2 lut entries and select for use. 1. determine location of bank 2 in lut. the first four entries in the 16 entry lut represent the first bank (bank 0). the following four entries in the lut rep- resent the second bank (bank 1), etc. consequently bank 2 starts at lut index 8 as shown below: monochrome (green) bank 2 is shown in figure 5. 2. write lut index to look-up table address register aux[0eh]. for bank 2, the index will one of the following values: 08h, 09h, 0ah, or 0bh 3. write lut entry value to look-up table data register aux[0fh]. for a linear lut, use the look-up table entries in table 3-8, ?s1d13503 black-to-white look-up table for 4 gray shades,? on page 26. 4. repeat steps 2 and 3 until all 4 lut entries have been written. 5. to display data using bank 2, write 10b to aux[0e] bits 7,6. table 3-8: s1d13503 black-to-white look-up table for 4 gray shades index (hex) look-up tab le (hex) 80 95 aa bf start of bank index bank number 4 = start of bank 2 2 4 8 ==
epson research and development page 27 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 4-level gray shade mode figure 5: 4-level gray-shade mode look-up table architecture green look-up table 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 bank select bits [1:0] (aux[0e] bits [7:6]) 4-bit display data output bank select logic note: the above depiction is intended to show the display data output path only. the cpu r/w access to the individual look-up tables is not affected by the various ?banking? configurations.
page 28 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2.5 four colors (two bits/pixel in color mode) when the s1d13503 is configured for two bit pixels in color mode, each pixel can index one of four color lut entries. the 16 lut entries are divided into four separate look-up tables or banks , each having four entries (see figure 6). the following examples show how to program and select these banks. example 7: in 4 color mode, program red bank 3 lut entries and select for use. 1. determine location of bank 3 in the red lut. the first four entries in the 16 entry lut represent the first bank (bank 0). the following four entries in the lut rep- resent the second bank (bank 1), etc. consequently bank 3 starts at lut index 0ch as shown below: red bank 3 is shown in figure 6. 2. write lut index and red lut selection to look-up table address register aux[0eh]. aux[0eh] = lut index ?or? 0001 0000b for bank 3, the index will one of the following values: 0ch, 0dh, 0eh, or 0fh, so the value written to aux[0eh] will be one of the following: 1ch, 1dh, 1eh, or 1fh. this selects the red lut only, indexes c, d, e and f. 3. write lut entry value to look-up table data register aux[0fh]. for a linear lut, use the look-up table entries in table 3-9, ?s1d13503 low to high intensity color look-up ta- ble for 4 colors,? on page 28. 4. repeat steps 2 and 3 until all 4 lut entries have been written. 5. to display data using red bank 3 write 11b to aux[0f] bits 7,6: aux[0fh] = original aux[0fh] ?or? 1100 0000b table 3-9: s1d13503 low to high intensity color look-up table for 4 colors index (hex) look-up tab le (hex) c0 d5 ea ff start of bank index bank number 4 = start of bank 3 3 4 12 0ch ===
epson research and development page 29 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 4-level color mode figure 6: 4-level color mode look-up table architecture 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 red bank select bits [1:0] (aux[0f] bits [7:6]) bank select logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 green bank select bits [1:0] (aux[0e] bits [7:6]) bank select logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 blue bank select bits [1:0] (aux[0f] bits [5:4]) bank select logic red look-up table green look-up table blue look-up table 4-bit ?green? 4-bit ?red? display data output display data output 4-bit ?blue? display data output
page 30 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2.6 sixteen gray shades (four bits/pixel in monochrome mode) when the s1d13503 has 4-bit monochrome pixels, each pixel can index into one of 16 lut entries. the lut bank bits are ignored in this mode. 16-level gray shade mode figure 7: 16-level gray-shade mode look-up table architecture 4-bit pixel data ( p3, p2, p1, p0 ) 4-bit look-up table data output msb lsb green look-up table 16x4 0 1 2 3 c d e f
epson research and development page 31 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 3.2.7 sixteen colors (four bits/pixel in color mode) when the s1d13503 has 4-bit color pixels, each pixel can index into each of the three color luts. the lut bank bits are ignored in this mode. 16-level color mode figure 8: 16-level color mode look-up table architecture table 3-10: simulation of first 16 entries of standard vga palette address red green blue address red green blue 00 00 00 00 08 00 00 00 01 00 00 0a 09 00 00 0f 02 00 0a 00 0a 00 0f 00 03 00 0a 0a 0b 00 0f 0f 04 0a 00 00 0c 0f 00 00 05 0a 00 0a 0d 0f 00 0f 06 0a 0a 00 0e 0f 0f 00 07 0a 0a 0a 0f 0f 0f 0f 4-bit pixel data red look-up table 16x4 0 1 2 3 c d e f green look-up table 16x4 0 1 2 3 c d e f blue look-up table 16x4 0 1 2 3 c d e f 4-bit ?red? look-up table data output 4-bit ?green? look-up table data output 4-bit ?blue? look-up table data output
page 32 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 3.2.8 256 colors (eight bits/pixel in color mode) when the s1d13503 has 8-bit color pixels, bits 7-5 represent the red lut index, bits 4-2 represent the green lut index, and bits 1-0 represent the blue lut index (see figure 9, ?256-level color mode look-up table architecture,? on page 33). it is recommended that the three luts are programmed according to table 3-5, ?s1d13503 color look-up table for 256 color mode,? on page 23, and only bank 0 were used for each of the three colors. this method results in each color index inside the pixel to represent its respective color intensity (see table 3-11 below). table 3-11: examples of 256 pixel colors using linear lut pixel value (binary) color pixel value (binary) color 000 000 00 black 000 000 00 black 000 000 10 dark blue 000 000 11 bright blue 000 100 00 dark green 000 111 00 bright green 000 100 10 dark cyan 000 111 11 bright cyan 100 000 00 dark red 111 000 00 bright red 100 000 10 dark magenta 111 000 11 bright magenta 100 100 00 dark yellow 111 111 00 bright yellow 100 100 10 gray 111 111 11 white
epson research and development page 33 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 256-level color mode figure 9: 256-level color mode look-up table architecture red look-up table 0 1 2 3 4 5 6 7 bank 0 0 1 2 3 4 5 6 7 bank 1 bank select logic 3-bit pixel data 0 1 2 3 4 5 6 7 bank 0 0 1 2 3 4 5 6 7 bank 1 bank select logic 3-bit pixel data 0 1 2 3 2-bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 bank 0 bank 1 bank 2 bank 3 blue bank select bits [1:0] (aux[0f] bits [5:4]) bank select logic blue look-up table green look-up table green bank select bit (aux[0e] bit 6) red bank select bit (aux[0f] bit 6) 76543210 r 2 r 1 r 0 g 2 g 1 g 0 b 1 b 0 256 color data format: 4-bit ?green? 4-bit ?red? display data output display data output 4-bit ?blue? display data output (r2, r1, r0) (g2, g1, g0) (b1, b0)
page 34 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 4 display memory models this section includes a concise description of the display start address registers, followed by a description of display memory. afterwards examples are provided, illustrating how to calculate the display memory model for a given display resolution and color/gray level mode. once this model is calculated, examples on programming the display start address registers are provided. 4.1 registers register bits discussed in this section are highlighted. bit 1 memory interface this bit selects between the 8-bit or 16-bit memory interface. when this bit = 0, the 16-bit memory inter- face is selected. when this bit = 1, the 8-bit memory interface is selected. if 16-bit bus interface (vd0 = 1 on reset) or 256 color mode (aux[03] bits 2-1 = 11) is selected, the memory interface bit is forced to 0 internally (16-bit). this bit goes low on reset. aux[06] bits 7-0 screen 1 display start address bits [15:0] aux[07] bits 7-0 these 16 bits determine the screen 1 display start address. in an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). in a 16-bit memory configuration these are the 16 most sig- nificant bits of a 17-bit start address (i.e., word access). note the absolute address into display memory is determined by the memory mapping address which is set by the reset state of vd13 - vd15. the screen 1 display start address is the memory address corresponding to the first displayed pixel (top left corner). in a dual panel configuration, screen 1 refers to the upper half of the display. while in a single panel configuration, screen 1 refers to the first screen of the split screen display feature where two differ- ent images (screen 1 and screen 2) can be displayed at the same time on one display. aux[01] mode register 0 i/o address = 0001b, read/write. disp panel mask xscl lcde gray shade / color lcd data width bit 0 memory interface rams aux[06] screen 1 display start address register (lsb) i/o address = 0110b, read/write. screen 1 display start addr bit 7 screen 1 display start addr bit 6 screen 1 display start addr bit 5 screen 1 display start addr bit 4 screen 1 display start addr bit 3 screen 1 display start addr bit 2 screen 1 display start addr bit 1 screen 1 display start addr bit 0 aux[07] screen 1 display start address register (msb) i/o address = 0111b, read/write. screen 1 display start addr bit 15 screen 1 display start addr bit 14 screen 1 display start addr bit 13 screen 1 display start addr bit 12 screen 1 display start addr bit 11 screen 1 display start addr bit 10 screen 1 display start addr bit 9 screen 1 display start addr bit 8
epson research and development page 35 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 aux[08] bits 7-0 screen 2 display start address bits [15:0] aux[09] bits 7-0 these 16 bits determine the screen 2 display start address. in an 8-bit memory configuration these bits set the 16-bit start address (i.e., byte access). in a 16-bit memory configuration these are the 16 most sig- nificant bits of a 17-bit start address (i.e., word access). in a dual panel configuration, screen 2 refers to the lower half of the display. the screen 2 display start address is the memory address corresponding to the first displayed pixel in the first line of the lower half of the display. if screen 2 is started right after screen 1, the screen 2 display start address can be calculated with the following formula: in a single panel configuration, screen 2 refers to the second screen of the split screen display feature where two different images (screen 1 and screen 2) can be displayed at the same time on one display. the screen 2 display start address is the memory address corresponding to the first pixel of the second image stored in display memory. to display screen 2 refer to aux[0a] screen 1 display line count register (lsb) on page 45. aux[08] screen 2 display start address register (lsb) i/o address = 1000b, read/write. screen 2 display start addr bit 7 screen 2 display start addr bit 6 screen 2 display start addr bit 5 screen 2 display start addr bit 4 screen 2 display start addr bit 3 screen 2 display start addr bit 2 screen 2 display start addr bit 1 screen 2 display start addr bit 0 aux[09] screen 2 display start address register (msb) i/o address = 1001b, read/write. screen 2 display start addr bit 15 screen 2 display start addr bit 14 screen 2 display start addr bit 13 screen 2 display start addr bit 12 screen 2 display start addr bit 11 screen 2 display start addr bit 10 screen 2 display start addr bit 9 screen 2 display start addr bit 8 screen 2 displaystartaddress hex () imagehorizontalresolution () imageverticalresolution () bytesperpixel () 2 memoryinterfacewidth 8 ---------------------------------------------------------------- ?? ?? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- screen 1 displaystartaddress + =
page 36 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 4.2 description when displaying an image, the s1d13503 must read pixel data from display memory. this memory is organized to match the display resolution of the given lcd panel. to organize display memory, the following registers must be programmed: 1. screen 1 display start address registers 2. screen 2 display start address registers 3. address pitch adjustment register for the first example, the address pitch adjustment register is programmed to zero. this means that no virtual display is available; for information on virtual displays see section 5.1, ?virtual displays? on page 40. 4.2.1 s5u13503b00c evaluation board display memory there are several issues to consider when programming the screen display start address registers for the s5u13503b00c evaluation board: the s5u13503b00c is always set for 128k of display memory. this memory exists as two 64k banks at addresses d000:0000h to d000:ffffh. to access bank 0, read from the base port address + 2. to access bank 1, write to base port address + 2. the values read from or written to base port address + 2 are not important. the start of bank 0 repre- sents the top left corner of display memory. for the s5u13503b00c, the screen display start address registers are always in reference to the display memory address d000:0000h, bank 0. writing 0 to a display start address register will always refer to d000:0000h, bank 0. although the s1d13503 can set the memory interface to 8 or 16 bits, the s5u13503b00c evaluation board must be set for 16 bits in order to access 128k of display memory. as a result, the display start address registers are word pointers, not byte pointers. to illustrate how to use a word pointer, refer to example 8. in general, any system which uses more than 64k of display memory must always have the memory interface set to 16 bits. example 8: for the s5u13503b00c, calculate the required start address register value which refers to location d000:0000h, bank 1. location d000:0000h bank 1 refers to the start of the second 64k bank of display memory. consequently the start address is 10000h bytes (64k), or 8000h words. start address[lsb] = 00h start address[msb] = 80h
epson research and development page 37 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 4.2.2 display start address registers this section illustrates how to properly calculate the values for the screen start address registers for a given lcd panel resolution. however, this section is limited to single panel displays; refer to section 5.4.3, ?dual panel lcd? on page 48 to program the screen start address registers for a dual panel display. in the following example, the display start address registers are programmed for a 16 color 320 x 240 single panel lcd display. the technique shown, however, can also be used to calculate the memory map of other resolutions. in addition, reference is made to the s5u13503b00c evaluation board; other hardware implementations of the s1d13503 may assign different display and port addresses from those of the s5u13503b00c. refer to the s5u13503b00c evaluation board user?s manual for more information on these hardware issues. example 9: program the display start address registers for a single lcd panel; the display is at- tached to the s5u13503b00c evaluation board. normally images are loaded at the start of display memory (d000:0000h, bank 0), so the display start address registers must be set to 0000h words. aux[06h] = 00h aux[07h] = 00h example 10: program the display start address registers for a dual panel lcd. refer to section 5.4.3.1, ?displaying a single image on a dual panel? on page 50. example 11: determine if the s1d13503 implementation can support a 640 x 480 lcd with 4 colors. 1. calculate the number of bytes per scan line: 2. calculate the total number of bytes required for display memory: 3. compare the required number of bytes with the amount of memory available to the s1d13503. the s1d13503 has 128k available, so there is 131,072 bytes available. since this number is greater than the 76,800 bytes required for 640 x 480 with 4 colors, the s1d13503 implementation can support a 640 x 480 lcd with 4 colors. note the memory required for 4 colors at 640 x 480 is the same as the memory required for 4 gray shades at 640 x 480. consequently the s1d13503 implementation can also support a 640 x 480 lcd with 4 gray shades. pixels per scan line pixels per byte --------------------------------------------- - 640 4 -------- - 160 bytes per scan line == 160 bytes per scan line () 480 scan lines () 76800 bytes =
page 38 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 4.3 common display memory requirements for lcd panel sizes: the following is a list of memory requirements and memory maps for common lcd resolutions. note that the memory required for 640 x 480 with 4 or 16 bits/pixel exceeds 128k and is therefore not supported on the s1d13503. figure 10: memory map example for 320 x 240 lcd panel with 4 colors/gray shades table 4-1: memory size requirements display resolution pixel storage memory requirements bits/pixel colors/ gray shades bytes hex 320 x 240 1 2 9,600 0000 2580 2 4 19,200 0000 4b00 4 16 38,400 0000 9600 8 256 76,800 0001 2c00 480 x 240 1 2 14,400 0000 3840 2 4 28,800 0000 7080 4 16 57,600 0000 e100 8 256 115,200 0001 c200 640 x 200 1 2 16,000 0000 3e80 2 4 32,000 0000 7d00 4 16 64,000 0000 fa00 8 256 128,000 0001 f400 640 x 480 1 2 38,400 0000 9600 2 4 76,800 0001 2c00 416n/an/a 8256n/an/a offset (hex) offset (hex) 0000 scan line 0 004f 0050 scan line 1 009f 4a60 scan line 238 4aaf 4ab0 scan line 239 4aff
epson research and development page 39 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 figure 11: memory map example for 320 x 240 lcd panel with 256 colors figure 12: memory map example for 640 x 200 lcd panel with 16 colors/gray shades offset (hex) offset (hex) 0000 0000 scan line 0 0000 013f 0000 0140 scan line 1 027f 0001 2980 scan line 238 0001 2abf 0001 2ac0 scan line 239 0001 2bff offset (hex) offset (hex) 0000 scan line 0 013f 0140 scan line 1 027f f780 scan line 198 f8bf f8c0 scan line 199 f9ff
page 40 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 5 advanced techniques this section presents information on the following: virtual displays bitmaps and text displays reading and writing to the s1d13503 registers split screen displays panning and scrolling power saving 5.1 virtual displays this section presents a detailed description of the address pitch adjustment register, followed by a description of a virtual display. afterwards an example is given, showing how to create a virtual display. 5.1.1 registers register bits discussed in this section are highlighted. bits 7-0 address pitch adjustment bits [7:0] this register controls the virtual display by setting the numerical difference between the last address of a display line, and the first address in the following line. if the address pitch adjustment is not equal to zero, then a virtual screen is formed. the size of the virtual screen is only limited by the available display memory. the actual display output is a window that is part of the whole image stored in the display memory. for example, with 128k of display memory, a 640x400 16-gray image can be stored. if the output display size is 320x240, then the whole image can be seen by changing display starting addresses through aux[06] and [07], and aux[08] and [09]. note that a virtual screen can be produced on either a single or dual panel. in 8-bit memory interface, if the address pitch adjustment is not equal to zero, a virtual screen with a line length of (line byte count +aux[0d]) bytes is created, with the display reflecting the contents of a win- dow (line byte count+1) bytes wide. the position of the window on the virtual screen is determined by aux[06] and [07], and aux[08] and [09]. in 16-bit memory interface, if the address pitch adjustment is not equal to zero, then a virtual screen with a line length of 2x(line byte count +aux[0d]) bytes is created, with the display reflecting the contents of a window 2x(line byte count+1) bytes wide. the position of the window on the virtual screen is deter- mined by aux[06] and [07], and aux[08] and [09]. aux[0d] address pitch adjustment register i/o address = 1101b, read/write. addr pitch adjustment bit 7 addr pitch adjustment bit 6 addr pitch adjustment bit 5 addr pitch adjustment bit 4 addr pitch adjustment bit 3 addr pitch adjustment bit 2 addr pitch adjustment bit 1 addr pitch adjustment bit 0
epson research and development page 41 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 5.1.2 description the s1d13503 can be programmed to wrap memory offsets in such a way that the physical display behaves as a viewport into a much larger ?virtual? memory space. this viewport can be panned and/or scrolled to display this larger memory space. referring to the figure below, a virtual image of 640x480 can be viewed by navigating the 320x240 viewport around the image by panning and scrolling. figure 13: moving a viewport inside a virtual display to create a virtual display, the address pitch adjustment register must be programmed to indicate the horizontal size of the larger, ?virtual? image stored in display memory. the address pitch adjustment register tells the s1d13503 how many bytes or words of display memory are part of the nonvisible region of display memory (see example 12). example 12: program the address pitch adjustment register to support a 16 color 640 x 480 virtual display on a 320 x 240 lcd panel; the memory interface is 16 bits. 1. initialize the s1d13503 registers for a 320x240 panel. 2. determine whether the address pitch adjustment register refers to bytes or words. since the memory interface is set to 16 bits, the address pitch adjustment register refers to words. 3. determine the number of pixels per unit referred to by the address pitch adjustment register. the address pitch adjustment register refers to units of words, so find the number of pixels per word. 4. calculate the number of pixels on a horizontal scan line not visible. consequently on a screen update the s1d13503 will show the first 320 of 640 pixels, and then ignore the remaining 320 pixels in order to reach the next scan line. 5. program the address pitch adjustment register therefore aux[0dh] = 50h 6. to view the rest of the image refer to section 5.5, ?panning and scrolling? on page 52, keeping in mind that the hor- izontal width is 640 pixels, not 320. 320x240 viewport 640x480 ?virtual? display 16 colors => 4 bits per pixel 4 bits per pixel => 2 pixels per byte pixels per word pixels per byte () 2 22 4 pixels per word === virtual display width in pixels () panel width in pixels () ? 640 320 ? 320 hidden pixels == number of hidden horizontal pixels pixels per word ----------------------------------------------------------------------------------- - 320 4 -------- - 80 words 50h words == =
page 42 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 5.2 bitmaps and text displays for the scope of this guide, a bitmap is a data structure which represents the image shown on the lcd. the bitmap includes the dimensions of the image, and the color or gray shade palette used to program the lookup table. text is shown by creating a font, which in this example is a series of bitmaps, one bitmap per alphanumeric character. example 13: display the word ?text? on a 256 color 320 x 240 lcd panel; the memory interface is 16 bits. 1. define the font for the letters ?t?, ?e?, and ?x?. each character is 8x8 pixels, with at least one horizontal and vertical side left blank for spacing. figure 14: font for the message ?text? 2. program the lookup table. see example 3, ?initialize the look-up table for 256 colors (bank 0 only),? on page 23. 3. calculate the display memory map. see figure 11, ?memory map example for 320 x 240 lcd panel with 256 colors,? on page 39. 4. write font to display memory. in a general purpose program the entire bitmapped font would be placed in an array. as characters are to be dis- played, the program would choose the appropriate bitmap, select the proper position on the screen, and write to dis- play memory. for this example assume that the program has already selected the proper bitmaps and the correct positions in display memory (there is a detailed programming example later in this guide; see section 7.3, ?advanced functions? on page 66). each highlighted pixel in the text bitmap will be shown at maximum intensity, which is pixel value 0ffh. the text, for simplicity, will be shown in the upper left corner of the screen. when the program has completed writing the pix- els for the word ?text?, the display memory will have the data shown in figure 15. in this figure the bytes are grouped within vertical lines.
epson research and development page 43 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 figure 15: display memory contents for message ?text? in 256 color mode 5.3 mapping of registers the s1d13503 has an internal set of 16-/8-bit read/write registers which configure it for various modes of operation. the registers can be accessed in two ways; indexed addressing and direct addressing. note refer to the s1d13503 hardware functional specification (document number x18a-a-001-xx) for more information on the s1d13503 registers. 5.3.1 indexed mapping this method requires only two sequential i/o address locations starting from the base i/o address. the base i/o address is determined by the power-on state of the sram data lines vd[4 through 12]. see ? summary of configuration options ? in the s1d13503 hardware functional specification , drawing office no. x18a-a-001-xx. the s5u13503b00c evaluation board uses three sequential i/o addresses which are defined as index address, index data, and memory banking. to access registers using this method, an index address must be written to the first i/o address location allowing data to be written/read to/from the second i/o address. the memory banking port is specific to the s5u13503b00c implementation and is used to select one of two 64k display memory banks; a read from this port selects bank 0, and a write to this port selects bank 1. note that the values read from or written to the memory banking port are not important. offset (hex) offset (hex) 0000 f f f f f f f f f f f f 0 0 0 0 f f f f f f f f f f f f f f 0 0 f f f f 0 0 0 0 0 0 f f f f 0 0 f f f f f f f f f f f f 0 0 0 0 001f 0140 f f 0 0 f f f f 0 0 f f 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 f f 0 0 f f f f 0 0 0 0 0 0 f f f f 0 0 f f 0 0 f f f f 0 0 f f 0 0 0 0 015f 0280 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 0 0 f f f f 0 0 f f 0 0 0 0 0 0 0 0 f f f f 0 0 f f f f 0 0 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 029f 03c0 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 0 0 f f f f f f f f 0 0 0 0 0 0 0 0 0 0 f f f f f f 0 0 0 0 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 03df 0500 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 0 0 f f f f 0 0 f f 0 0 0 0 0 0 0 0 0 0 f f f f f f 0 0 0 0 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 051f 0640 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 f f 0 0 0 0 f f f f 0 0 f f f f 0 0 0 0 0 0 0 0 f f f f 0 0 0 0 0 0 0 0 065f 0780 0 0 f f f f f f f f 0 0 0 0 0 0 f f f f f f f f f f f f f f 0 0 f f f f 0 0 0 0 0 0 f f f f 0 0 0 0 f f f f f f f f 0 0 0 0 0 0 079f 08c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 08df
page 44 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 example 14: write 12h to register 08h on the s5u13503b00c evaluation board; the base port address is 310h, and indexed port mapping is used. 1. write 08h to the index register the index register is at base port address + 0 = 310h. mov dx,310h mov al,08h out dx,al 2. write 12h to the data register the data register is at base port address + 1 = 311h. mov dx,311h mov al,12h out dx,al 5.3.2 direct mapping this method of addressing requires 16 sequential i/o addresses starting from the base i/o address. the base i/o address is determined by the power-on state of the sram data lines vd[7 through 12]. see ? summary of configuration options ? in the s1d13503 hardware functional specification , drawing office no. x18a-a-001-xx. to access the internal 16 registers of the s1d13503, simply perform i/o read/write functions to the absolute address as defined in the previous paragraph. there is no memory banking available in direct addressing mode. example 15: write 12h to register 08h on the s5u13503b00c evaluation board; the base port address is 310h, and direct port mapping is used. 1. calculate the port address for register 08h. 2. write the value 12h to port address 318h. mov dx,318h mov al,12h out dx,al note the s5u13503b00c is normally configured for indexed mapping, not direct mapping. refer to the s5u13503b00c evaluation board user?s manual for more information configuring the s5u13503b00c board for indexed or direct mapping. port address 310h 8h + 318h ==
epson research and development page 45 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 5.4 split screen this section describes how to create a split screen for both single and dual lcd panels. for single panel displays, the screen 1 display line count registers are used. for dual panel displays, the screen 2 display start address registers are used. registers aux[0a] bits 7-0 screen 1 display line count bits [9:0] aux[0b] bits 1-0 these bits are the eight lsb of a 10-bit value used to determine the number of lines displayed for screen 1. the remaining lines will automatically display from the screen 2 display start address. the 10-bit value programmed is the number of display lines -1. this register is used to enable the split screen display feature (single panel only) where two different images can be displayed at the same time on one display. for example; aux[0a] = 20h for a 320x240 display system. the display will display 20h+1 = 33 lines on the upper part of the screen as dictated by the screen 1 display start address registers (aux[06] and aux[07]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the screen 2 display start address registers (aux[08] and aux[09]). two different images can be displayed when using a dual panel configuration by changing the screen 2 dis- play start address. however, by using this method screen 2 is limited to the lower half of the display. this register is ignored in dual panel mode. note see section 4.2.2, ?display start address registers? on page 37 for additional register descriptions. 5.4.1 description a split screen is generally considered as the presentation of two different images on the screen. image 1 is shown on the top half and image 2 is shown on the bottom half of the screen. the system is always in split screen mode, on a single panel image 2 is displayed off screen; on a dual panel image 2 becomes the lower half of the panel. aux[0a] screen 1 display line count register (lsb) i/o address = 1010b, read/write. screen 1 display line count bit 7 screen 1 display line count bit 6 screen 1 display line count bit 5 screen 1 display line count bit 4 screen 1 display line count bit 3 screen 1 display line count bit 2 screen 1 display line count bit 1 screen 1 display line count bit 0 aux[0b] screen 1 display line count register (msb) i/o address = 1011b, read/write. n/a n/a n/a n/a n/a n/a screen 1 display line count bit 9 screen 1 display line count bit 8
page 46 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 5.4.2 single panel lcd the following is the procedure to show a split screen image on a 16 color 320 x 240 single panel lcd. for this example the s5u13503b00c is used with the memory interface set to 16 bits (required for 128k of display memory). in addition, the two images shown on the split screen are each 320 x 240; only a portion of each image is shown. 1. determine whether the display start address registers refer to bytes or words. since the memory interface is set to 16 bits, the display start address registers refer to words. note that when ad- dresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). 2. calculate the number of bytes per scan line. 3. determine the display memory location for image 1. for simplicity, assign the beginning of display memory as the starting address of image 1 (see figure 16). for the s5u13503b00c, this address is d000:0000h, bank 0. figure 16: memory map for split screen 4. program the screen 1 display start address register to point to the beginning of image 1. since image 1 is at the beginning of display memory, program the screen 1 display start address register to 0000h. aux[06h] = 00h aux[07h] = 00h 5. calculate the total number of bytes required for image 1. display memory screen 1 display start address image 1 d000:0000h, bank 0 screen 2 display start address image 2 d000:9600h, bank 0 (for this example) 16 colors => 4 bits per pixel 4 bits per pixel => 2 pixels per byte number of bytes per scan line pixels per scan line pixels per byte --------------------------------------------- - 320 2 -------- - 160 bytes per scan line 00a0h bytes per scan line === = bytes per scan line () number of scan lines for image 1 () 160 240 38400 bytes 9600h bytes == =
epson research and development page 47 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 6. determine the display memory location for image 2. place image 2 immediately after image 1 (see figure 16). assign the starting address for image 2 as follows: note that if the image 2 address is larger than d000:ffffh, then switch to bank 1, reset the segment to d000h, and keep the offset. for example, if the image 2 address were {d001:9200h, bank 0}, then this address must be changed to {d000:9200h, bank 1}. 7. program the screen 2 display start address register to point to the beginning of image 2. image 2 is placed right after image 1, as shown below: aux[08h] = 00h aux[09h] = 4bh 8. program the screen 1 display line count register. the display line count register indicates how many lines of the first screen should be shown minus 1 . by changing the line count, image 2 appears to move up or down the display. if the line count is set to the maximum number of visible scan lines - 1, only image 1 is shown. aux[0ah] = lsb of (visible scan lines - 1) = efh aux[0bh] = msb of (visible scan lines - 1) = 00h if the line count is set to 0, then the first scan line of image 1 is shown followed by the first part of image 2. it is not possible to show only image 2 by changing the line count. if only image 2 needs to be shown, reprogram the screen 1 display start address registers to point to the beginning of image 2. once both screen 1 and 2 display start address registers point to the same image, the line count has no visible effect. aux[0ah] = 00h aux[0bh] = 00h image 2 address base display memory address () size of image 1 () + = d000:0000h, bank 0 {} 0000:9600h + = d000:9600h, bank 0 {} = screen 2 display start address screen 1 display start address size of image 1 in bytes 2 bytes per word -------------------------------------------------------- + = 0000h 9600h 2 -------------- - +4b00h == visible scan lines 1 ?2401 ? 239 00efh ===
page 48 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 if the line count is set to 99, then the first 100 scan lines of image 1 are shown, following by the first part of im- age 2 (see figure 17). aux[0ah] = 63h (99 decimal) aux[0bh] = 00h figure 17: 320 x 240 single panel for split screen 9. write both image 1 and image 2 to their respective locations in display memory. 5.4.3 dual panel lcd the following is the procedure to show a split screen image on a 4 gray shade 640 x 480 dual panel lcd. for this example the s5u13503b00c is used with the memory interface set to 16 bits (required for 128k of display memory). in addition, the two images shown on the split screen are each 640 x 240. 1. determine whether the display start address registers refer to bytes or words. since the memory interface is set to 16 bits, the display start address registers refer to words. note that when ad- dresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). 2. calculate the number of bytes per scan line. 3. determine the display memory location for image 1. for simplicity, assign the beginning of display memory as the starting address of image 1 (see figure 16). for the s5u13503b00c, this address is d000:0000h, bank 0. 4. program the screen 1 display start address register to point to the beginning of image 1. since image 1 is at the beginning of display memory, program the screen 1 display start address register to 0000h. aux[06h] = 00h aux[07h] = 00h 5. calculate the total number of bytes required for image 1. scan line 0 image 1 ... scan line 99 scan line 100 image 2 ... scan line 239 screen 1 display line count register = 99 lines 4 gray shades => 2 bits per pixel 2 bits per pixel => 4 pixels per byte number of bytes per scan line pixels per scan line pixels per byte --------------------------------------------- - 640 4 -------- - 160 bytes per scan line 00a0h bytes per scan line === = bytes per scan line () number of scan lines for image 1 () 160 240 38400 bytes 9600h bytes == =
epson research and development page 49 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 6. determine the display memory location for image 2. place image 2 immediately after image 1 (see figure 16). assign the starting address for image 2 as follows: note that if the image 2 address is larger than d000:ffffh, then switch to bank 1, reset the segment to d000h, and keep the offset. for example, if the image 2 address were {d001:9200h, bank 0}, then this address must be changed to {d000:9200h, bank 1}. 7. program the screen 2 display start address register to point to the beginning of image 2. image 2 is placed right after image 1, as shown below: aux[08h] = 00h aux[09h] = 4bh 8. write both image 1 and image 2 to their respective locations in display memory. notes when using a dual panel, the screen 1 display line count register is ignored by the s1d13503. once the two display start address registers are programmed, the top panel will show the beginning of image 1, and the bottom panel will show the beginning of image 2 (see figure 18). figure 18: 640 x 480 dual panel for split screen scan line 0 image 1 ... scan line 239 scan line 240 image 2 ... scan line 479 screen 1 display line count is ignored; image 1 always has half the total number of scan lines (240 in this example). image 2 address base display memory address () size of image 1 () + = d000:0000h, bank 0 {} 0000:9600h + = d000:9600h, bank 0 {} = screen 2 display start address screen 1 display start address size of image 1 in bytes 2 bytes per word -------------------------------------------------------- + = 0000h 9600h 2 -------------- - +4b00h ==
page 50 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 each image can be scrolled or panned by appropriate programming of the respective display start address registers. the following are some examples: to scroll image 1 up, the screen 1 start address register must point to the following scan line. aux[06h] = lsb of screen 1 display start address aux[07h] = msb of screen 1 display start address to scroll image 2 down, the screen 2 start address register must point to the previous scan line. aux[08h] = lsb of screen 2 display start address aux[09h] = msb of screen 2 display start address to pan image 1 to the right by a group of pixels, the screen 1 start address register must be increased by 1. aux[06h] = lsb of screen 1 display start address aux[07h] = msb of screen 1 display start address see section 5.5.2, ?panning right and left? on page 52 for more information. to pan image 2 to the left by a group of pixels, the screen 2 start address register must be decreased by 1. aux[08h] = lsb of screen 2 display start address aux[09h] = msb of screen 2 display start address see section 5.5.2, ?panning right and left? on page 52 for more information. 5.4.3.1 displaying a single image on a dual panel the following is the procedure to show a single image on a dual panel lcd. in this procedure the single image is broken into two smaller images; the first half of the image is placed on the top panel and the second half is placed on the bottom panel. for this example the s5u13503b00c is used with a 4 gray shade 640 x 480 dual panel lcd; the memory interface is set to 16 bits to support 128k of display memory. 1. determine whether the display start address registers refer to bytes or words. since the memory interface is set to 16 bits, the display start address registers refer to words. note that when ad- dresses refer to words, the image must be aligned in memory such that the beginning is found on a word boundary (the least significant bit of the memory address must be 0). 2. calculate the number of bytes per scan line. screen 1 display start address screen 1 display start address number of bytes per scan line 2 bytes per word ---------------------------------------------------------------------- + = screen 2 display start address screen 2 display start address number of bytes per scan line 2 bytes per word ---------------------------------------------------------------------- ? = screen 1 display start address screen 1 display start address 1 + = screen 2 display start address screen 2 display start address 1 ? = 4 gray shades => 2 bits per pixel 2 bits per pixel => 4 pixels per byte number of bytes per scan line pixels per scan line pixels per byte --------------------------------------------- - 640 4 -------- - 160 bytes per scan line 00a0h bytes per scan line === =
epson research and development page 51 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 3. determine the display memory location for the first half of the image. for simplicity, assign the beginning of display memory as the starting address of the image?s first half (see figure 19). for the s5u13503b00c, this address is d000:0000h, bank 0. figure 19: memory map for a dual panel showing a single image 4. program the screen 1 display start address register to point to the beginning of the first half of the image. since the first half is at the beginning of display memory, program the screen 1 display start address register to 0000h. aux[06h] = 00h aux[07h] = 00h 5. determine the size of the image?s first half. 6. determine the display memory location for the second half of the image. place the second half of the image immediately after the first half (see figure 19). assign the starting address for the second half as follows: note that if the address of the second half of the image is larger than d000:ffffh, then switch to bank 1, reset the segment to d000h, and keep the offset. for example, if the address of the second half of the image were {d001:9200h, bank 0}, then this address must be changed to {d000:9200h, bank 1}. display memory screen 1 display start address first half of image screen 2 display start address second half of image vertical size of first half of image vertical size of panel 1 number of scan lines in display 2 -------------------------------------------------------------------------- = 480 2 -------- - 240 scan lines === size display width in pixels pixels per byte ------------------------------------------------------ number of scan lines in first half of image () 640 4 -------- - 240 38400 bytes 9600h bytes ==== address of second half of image base display memory address () size of first half of image () + = d000:0000h, bank 0 {} 0000:9600h + = d000:9600h, bank 0 {} =
page 52 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 7. program the screen 2 display start address register to point to the beginning of the second half of the image. the second half of the image is placed right after the first half, as shown below: aux[08h] = 00h aux[09h] = 4bh 8. write both the first and second halves of the image to their respective locations in display memory. 5.5 panning and scrolling panning and scrolling are typically used to show an image which is too large to be shown completely on an lcd panel. although the image is stored entirely in display memory, only a small portion is actually visible on the lcd panel. this visible portion is called the viewport ; the user moves this viewport over different portions of the image by panning and scrolling. panning moves the viewport right or left. scrolling moves the viewport up or down. 5.5.1 initialization to pan and scroll over a large image, the s1d13503 registers must first be initialized and the image written to display memory. to do so, initialize the registers as described in section 2, ?initializing the s1d13503? on page 10, but with the following exception: the address pitch adjustment register in the s1d13503 must be set to create a virtual display; see section 5.1, ?virtual displays? on page 40 for more information. 5.5.2 panning right and left to pan to the right, increase the value in the screen 1 display start address register. to pan to the left, decrease the value in the screen 1 display start address register. note that the s1d13503 can pan right or left by either 1, 2, 4, 8, or 16 pixels. this is because the screen 1 display start address register refers to either bytes or words (see section 4.2.1, ?s5u13503b00c evaluation board display memory? on page 36), and a byte can represent 1, 2, 4, or 8 pixels, and so a word can represent 2, 4, 8, or 16 pixels; see table 5-1 below: table 5-1: smallest number of pixels for panning memory interface colors/ gray levels pixels per byte smallest number of pixels for panning 8 bits 28 8 44 4 16 2 2 256 1 1 16 bits 28 16 44 8 16 2 4 256 1 2 screen 2 display start address register screen 1 display start address register size of first half of image in bytes 2 bytes per word -------------------------------------------------------------------------------- + = 0000h 9600h 2 -------------- - +4b00h ==
epson research and development page 53 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 5.5.3 scrolling up and down to scroll up, increase the value in the screen 1 display start address register by the number of bytes in one virtual scan line. to scroll down, decrease the value in the screen 1 display start address register by the number of bytes in one virtual scan line. a virtual scan line is in reference to a virtual display, in which an image larger than the physical size of the lcd is stored. the number of bytes in a virtual scan line is the number of bytes required to store one horizontal line of pixels in the virtua l image. example 16: scroll down one line for a 16 gray shade 640 x 200 virtual image using a 320 x 240 single panel lcd. the memory interface is set to 16 bits to support 128k of display memory. also describe how to scroll in a dual panel lcd. 1. calculate the number of bytes in a virtual scan line. 2. add the number of words in a virtual scan line to the screen 1 display start address register. in this example the screen 1 display start address points to the beginning of the image. 3. program the screen 1 display start address. aux[06h] = a0h aux[07h] = 00h 4. this step is for dual panels only. add the number of words in a virtual scan line to the screen 2 display start address register. in this example the screen 2 display start address has previously been initialized as described in section 5.4.3.1, ?displaying a single image on a dual panel? on page 50. 5. this step is for dual panels only. program the screen 2 display start address. aux[08h] = least significant byte of ?screen 2 display start address? aux[09h] = most significant byte of ?screen 2 display start address? number of horizontal pixels in virtual image number of pixels per word --------------------------------------------------------------------------------------------------------- - 640 pixels per scan line 2 pixels per byte -------------------------------------------------------- 3 2 0 b y t e s p e r s c a n l i n e == screen 1 display start address screen 1 display start address number of bytes in a virtual scan line 2 bytes per word ---------------------------------------------------------------------------------------- - + = 0000h 320 2 -------- - + = 00a0h = screen 2 display start address screen 2 display start address number of bytes in a virtual scan line 2 bytes per word ---------------------------------------------------------------------------------------- - + =
page 54 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 5.6 power saving the following section introduces the power saving capabilities of the s1d13503. a detailed description of the power save register is provided, followed by a description of the power save modes. 5.6.1 registers register bits discussed in this section are highlighted. bits 7-6 ps bits [1:0] selects the power save modes as shown in the following table. the ps bits [1:0] go low on reset. for more details refer to ? power save modes ? in the s1d13503 hardware functional specification , draw- ing office no. x18a-a-001-xx. 5.6.2 power save modes two software-controlled power save modes have been incorporated into the s1d13503 to accommodate the important need for power reduction in the hand-held devices market. these modes can be enabled by setting the 2 power save bits (aux[03h] bits 7-6). the various settings are: 5.6.2.1 power save mode 1 power save mode 1 would typically be used when power savings are required and display memory accesses may occur. the disadvantage is that since the oscillator is running, this mode consumes more power that power save mode 2. 5.6.2.2 power save mode 2 power save mode 2 is typically used when display memory accesses would not occur. aux[03] mode register 1 i/o address = 0011b, read/write ps bit 1 ps bit 0 lcd signal state lut bypass lcd data width bit 1 bw / 256 colors color mode line byte count bit 8 table 5-2: power save mode selection ps1 ps0 mode activated 0 0 normal operation 0 1 power save mode 1 1 0 power save mode 2 11 reserved table 5-3: power save mode selection bit 7 bit 6 mode activated 0 0 normal operation 0 1 power save mode 1 1 0 power save mode 2 11 reserved
epson research and development page 55 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 5.6.2.3 power save mode function summary note 1. when programming the ps bits perform a read/modify/write operation so as not to destroy any other data in the register. 2. refer to the programming example in advanced functions on page 66. 5.6.2.4 programming to enter power down mode if the lcdenb pin is used to control an external lcdbias power supply, the following sequence is recommended to prevent damage to the panel. panel damage can occur if the lcdbias is present without active panel sync signals. note the lcdenb pin is controlled by aux[01h] bit 4 (lcde). 1. write ?0? to bit 7 of aux[01h] to turn off the display. 2. write to bit 4 of aux[01h] with value 'x' as appropriate to disable the specific power supply design. for the s5u13503b00c, write ?0? to disable the power supply. 3. wait until the lcdbias power supply reaches zero volts. this delay time is dependent upon the specific power sup- ply design, as well as the display?s electrical characteristics. for the s5u13503b00c, this time is about 0.5 seconds. 4. enter power saving mode by writing the appropriate bits 7-6 of aux[03h]. 5.6.2.5 programming to exit power down mode when the lcdenb pin is used to control an external lcdbias power supply, the following sequence is recommended to exit power down mode. note the lcdenb pin is controlled by aux[01h] bit 4 (lcde). 1. exit power saving mode by writing 00b to bits 7-6 of aux[03h]. 2. write to bit 4 of aux[01h] with value 'x' as appropriate to enable the specific power supply design. for the s5u13503b00c, write ?1? to enable the power supply. note that no delay is required before applying power. 3. write ?1? to bit 7 of aux[01h] to turn on the display. table 5-4: power save mode function summary function power save mode (psm) normal (active) psm1 psm2 state 1 state 2 display active? yes no no no i/o access possible? yes yes yes yes memory access possible? yes yes no no sequence controller running? yes no no no internal oscillator disabled? no no no yes
page 56 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 6 identifying the s1d13503 to identify the lcd controller upon power up / reset, perform the following steps: 1. power up lcd controller. 2. read aux[0eh], bits 5-4. refer to table 6-1 below to decode chip id. note if the registers have already been initialized after power up, the id bits in aux[0eh] cannot be used since these bits are also used for the rgb index. it is recommended to always store the chip id immedi- ately after power up and before any register initialization. table 6-1: id bit usage chip aux[0e] bit 5 bit 4 power on or reset s1d13503 0 0 reserved 0 1 s1d13502 1 0 s1d13502 1 1
epson research and development page 57 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 7 programming the s1d13503 the purpose of this section is to show how to program the s1d13503 exercising the specific capabilities of this chip. a series of functions written in ?c? will be presented, each illustrating a basic feature of the s1d13503. these functions are written for the s5u13503b00c evaluation board, and are combined under a menu-driven program called 13503demo.exe. note the sample code will not run on a display larger than 320 x 240, and will use either 256 colors or 16 gray shades in most of the examples. this program accepts the following command line options: 13503demo t=n x=n y=n d=n i=n p=n [f=n] [/?] for example, if there is a 320 x 240 color single panel lcd, 8 bit interface, format 2, with a port address of 310h, type 13503demo t=single x=320 y=240 d=color i=8 p=310 f=2 when 13503demo is started, output will be sent to the standard output device. this output will present a menu of numbered options: figure 20: display for 13503demo.exe where: t = single | dual x = horizontal panel size in pixels from 1 to 320 (decimal) y = vertical panel size in pixels from 1 to 240 (decimal) d = color | mono i = 4 | 8 (4 bit or 8 bit interface to panel) p = 300 | 310 ... 360 | 370 (port address in hex) (indexed i/o addressing selected by default) f = 1 | 2 (format for color 8 bit panel interface) /? = show this help screen s1d13503/s5u13503b00c demo program press 1 to read registers press 2 to show color/gray shade bar press 3 to show split screen press 4 to show panning and scrolling press 5 to start power saving press esc to quit
page 58 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 7.1 main loop code //------------------------------------------------------------------------- // // function: main() // // description: start of demo program. // // inputs: command line arguments. // return value: none. // //------------------------------------------------------------------------- void main(char argc, char **argv) { int ch; checkarguments(argc, argv); printf("initializing\n"); initialize(); setdisplay(off); clearlcdscreen(); switch (getid(panelportaddr)) { case id_13502: printf("detected s1d13502.\n\n"); quit(); break; case id_13502: printf("detected s1d13502.\n\n"); quit(); break; case id_13503: printf("detected s1d13503.\n"); break; default: printf("error: could not detect chip.\n\n"); quit(); break; } showmenu(); while ((ch = getch()) != esc) { switch (ch) { case '1': showregisters();
epson research and development page 59 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 break; case '2': grayshadebars(); break; case '3': splitscreen(); break; case '4': panscroll(); break; case '5': powersaving(); break; case esc: exit(0); } } }
page 60 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 7.2 initialization code //------------------------------------------------------------------------- // // function: initialize() // // description: intialize s1d13503 registers. // // inputs: this function looks at the followingl global variables to // determine the appropriate register settings: // panelx, panely, paneltype // // outputs: the following global variables are changed: // panelgraylevel, bytesperscanline // //------------------------------------------------------------------------- void initialize(void) { static unsigned int val, val2; static unsigned int x; if (paneld == panel_mono) panelgraylevel = 16; else panelgraylevel = 256; //-------------------------------------- // // mode register: // display = off // panel = single // mask xscl = not masked // lcde = not enabled // gray shade/color = 16 gray shades (bit is ignored for 256 colors) // lcd data width = 8 bit data transfer // memory interface = 16 bits // rams = addressing for 8kx8 sram // val = 0x0c; if (interface == 4) val &= 0xfb; // clear aux[01] bit 2 so that memory interface = 4 bits if (paneltype == type_dual) val |= 0x40; // set panel type to dual writeregister(1, val); // write to mode register //--------------------------------------
epson research and development page 61 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 // // line byte/word count register // // bits 0-7 are in aux[2], bit 8 is in aux[3]. // // because the memory interface is set to 16 bits, the // line byte/word count register counts in words. // to calculate the line byte count for different numbers of // gray shades/colors, use the following formula: // // bitsperpixel // ---------------------- x horizontal resolution - 1 // memory interface width // switch (panelgraylevel) { case 2: val = (panelx / 16) - 1; // for black and white mode break; case 4: val = (panelx / 8) - 1; // for 4 gray shades/colors break; case 16: val = (panelx / 4) - 1; // for 16 gray shades/colors break; case 256: val = (panelx / 2) - 1; // for 256 colors break; } writeregister(2, val & 0xff); // line byte/word count register val2 = (val >> 8) & 0x01; if (paneld == panel_color) { val2 |= 0x06; // select color mode and 256 colors if ((interface == 8) && (panelf == 2)) val2 |= 0x08; // select format 2 } writeregister(3, val2); // mode register 1 // // bytesperscanline is a global variable // switch (panelgraylevel) {
page 62 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 case 2: bytesperscanline = (panelx / 8); break; case 4: bytesperscanline = (panelx / 4); break; case 16: bytesperscanline = (panelx / 2); break; case 256: bytesperscanline = panelx; break; } //-------------------------------------- // // total display line count register // screen 1 display line count register // // to show a full image on screen 1, copy the total display line count // into the screen 1 display line count. // // // old programs had previously assumed that all panels smaller // than 400 lines use a 4 bit interface. however, newer panels // which are less than 400 lines may use an 8 bit interface. // consequently this program must be told which interface to use. // // set the mask xscl bit to masked (1) when using a 4 bit interface. // if (interface == 4) { val = readregister(1); val &= 0xfb; // set lcd data width to 4 bit data transfer val |= 0x20; // set mask xscl to masked writeregister(1, val); // write to mode register; lcd data width = 4 bits } val = panely; // // a dual panel lcd will, of course, have two panels. each panel will // show either the top or bottom half of the image, which is half of the // vertical resolution. // if (paneltype == type_dual) val /= 2;
epson research and development page 63 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 --val; writeregister(4, val & 0xff); // write to total display line count reg writeregister(0x0a, val & 0xff); // write to screen 1 display line count reg writeregister(5, (val >> 8) & 0x03); // total disp line cnt (msb)/wf count reg writeregister(0x0b, (val >> 8) & 0x03); // scrn 1 disp line count reg (msb) //-------------------------------------- // // set screen 1 display start address to beginning of video memory // writeregister(6, 0); // write to screen 1 display start address register writeregister(7, 0); //-------------------------------------- // // screen 2 display start address register // // if using a dual panel, the screen 2 display start address must point // to the second half of the image in video memory. // if (paneltype == type_dual) { val = (unsigned int) ((readregister(3) & 0x01) << 8) | readregister(2); ++val; val *= (panely / 2); writeregister(8, val & 0xff); writeregister(9, val >> 8); } else { // // on a single panel, screen 1 was programmed to show all of its // lines. consequently screen 2 will not be seen, and so the // screen 2 display start address will have no observable effect. // for convenience, set the screen 2 address to 0. // writeregister(8, 0); writeregister(9, 0); } //-------------------------------------- // // set horizontal non-display period to 0 to use fixed default non-display period // writeregister(0x0c, 0); //--------------------------------------
page 64 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 // // set address pitch adjustment to 0 // writeregister(0x0d, 0); // write to address pitch adjustment register //-------------------------------------- // // update lookup table for 16 gray shades/ 256 colors // if (paneld == panel_mono) { for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, monolut16[x]); } } else { for (x = 0; x < 16; ++x) { writeregister(0x0e, x); // auto-increment mode selected writeregister(0x0f, colorlut256red[x]); writeregister(0x0f, colorlut256green[x]); writeregister(0x0f, colorlut256blue[x]); } } //-------------------------------------- // // now that system is initialized, set display on and enable lcde // val = readregister(1); val |= 0x90; // display on, lcde enabled writeregister(1, val); } //------------------------------------------------------------------------- // // getid() // // this function returns the chip id. // //------------------------------------------------------------------------- static unsigned char getid(int portaddr) { static unsigned char chipid;
epson research and development page 65 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 chipid = id_not_detected; // // if the chip was just powered up, and no registers have been initialized, // then use the following code: // outp(portaddr, 0x0e); switch (inp(portaddr+1) & 0x30) { case 0x00: chipid = id_13503; break; case 0x20: chipid = id_13502; break; case 0x30: chipid = id_13502; break; default: chipid = id_not_detected; break; } return(chipid); }
page 66 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 7.3 advanced functions #define virtual_x (360l) #define virtual_y (360l) //------------------------------------------------------------------------- // // function: showregisters() // // description: shows the contents of the s1d13503 registers. // // inputs: none. // return value: none. // //------------------------------------------------------------------------- void showregisters(void) { static unsigned char x; static unsigned char red, green, blue; printf("s1d13503 registers: "); for (x = 0; x < 16; ++x) printf("%02x ", readregister(x)); printf("\ns1d13503 lookup table: "); for (x = 0; x < 16; ++x) { writeregister(0x0e, x); red = readregister(0x0f); green = readregister(0x0f); blue = readregister(0x0f); if (x % 7 == 0) printf("\n"); printf("(%02x,%02x,%02x) ", red, green, blue); } showmenu(); } //------------------------------------------------------------------------- // // function: grayshadebars() // // description: displays a series of vertical bars, each with a // different color/gray shade. // for color displays, bars are shown for 4, 16, and 256 colors.
epson research and development page 67 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 // for monochrome displays, bars are shown for black and white, // 4, and 16 gray shades. // // inputs: none. // // return value: none. // //------------------------------------------------------------------------- void grayshadebars(void) { static unsigned int val, val2, x; static unsigned char _far *pvideo; static char gray4[] = "vertical bars at 4 gray shades"; static char color4[] = "vertical bars at 4 colors"; static char gray16[] = "vertical bars at 16 gray shades"; static char color16[] = "vertical bars at 16 colors"; static char *str; printf("displaying vertical bars\n"); initialize(); setdisplay(off); clearlcdscreen(); // // access memory banks // fp_seg(pvideo) = 0xd000; fp_off(pvideo) = 0x0000; //-------------------------------------- if (paneld == panel_mono) { // // select black and white mode // val = readregister(3); val |= 0x04; // set aux[03] bit 2 val &= 0xfd; // clear aux[03] bit 1 writeregister(3, val); // // update line byte/word count register for black and white. // // since black and white has 8 pixels per byte, there
page 68 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 // are ((x horizontal pixels)/8) bytes per scan line. this means that // there are ((x horizontal pixels)/16) words per scan line. // // since the memory interface is set to 16 bits, the line byte/word count // refers to words. // val = (panelx / 16) - 1; bytesperscanline = (panelx / 8); writeregister(2, val & 0xff); // line byte count register val2 = readregister(3); val2 &= 0xfe; // clear bit 0 val2 |= (val >> 8) & 0x01; writeregister(3, val2); // mode register 1 panelgraylevel = 2; showverticalbars(pvideo, 0); // // show text. the lightest gray shade is set to panelgraylevel-1. // showtext(pvideo, bank0, "vertical bars for black and white", panelgraylevel-1); setdisplay(on); delay(2000); } //-------------------------------------- setdisplay(off); clearlcdscreen(); // // select 4 gray shades/colors // if (paneld == panel_mono) { val = readregister(1); val &= 0xf7; // clear aux[01] bit 3 writeregister(1, val); val = readregister(3); val &= 0xf9; // clear aux[03] bits 1 and 2 writeregister(3, val); // // update lookup table for 4 gray shades // for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, monolut4[x]); }
epson research and development page 69 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 str = gray4; } else // 4 colors { val = readregister(1); val &= 0xf7; // clear aux[01] bit 3 writeregister(1, val); val = readregister(3); val &= 0xfb; // clear aux[03] bit 2 val |= 0x02; // set aux[03] bit 1 writeregister(3, val); // // update lookup table for 4 colors // for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, colorlut4red[x]); writeregister(0x0f, colorlut4green[x]); writeregister(0x0f, colorlut4blue[x]); } str = color4; } // // update line byte/word count register for 4 colors/gray shades // // since 4 colors/gray shades corresponds to 4 pixels per byte, there // are ((x horizontal pixels)/4) bytes per scan line. this means that // there are ((x horizontal pixels)/8) words per scan line. // // since the memory interface is set to 16 bits, the line byte/word count // refers to words. // val = (panelx / 8) - 1; bytesperscanline = (panelx / 4); writeregister(2, val & 0xff); // line byte count register val2 = readregister(3); val2 &= 0xfe; // clear bit 0 val2 |= (val >> 8) & 0x01; writeregister(3, val2); // mode register 1 panelgraylevel = 4; showverticalbars(pvideo, 0); //
page 70 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 // show text. the lightest color/gray shade is set to panelgraylevel-1. // showtext(pvideo, bank0, str, panelgraylevel-1); showtext(pvideo + bytesperscanline*8, bank0, "bank: 0", panelgraylevel-1); setdisplay(on); delay(2000); val = readregister(0x0e); val &= 0x3f; val |= 0x40; writeregister(0x0e, val); showverticalbars(pvideo, 0); showtext(pvideo, bank0, str, panelgraylevel-1); showtext(pvideo + bytesperscanline*8, bank0, "bank: 1", panelgraylevel-1); delay(2000); val &= 0x3f; val |= 0x80; writeregister(0x0e, val); showverticalbars(pvideo, 0); showtext(pvideo, bank0, str, panelgraylevel-1); showtext(pvideo + bytesperscanline*8, bank0, "bank: 2", panelgraylevel-1); delay(2000); val |= 0xc0; writeregister(0x0e, val); showverticalbars(pvideo, 0); showtext(pvideo, bank0, str, panelgraylevel-1); showtext(pvideo + bytesperscanline*8, bank0, "bank: 3", panelgraylevel-1); delay(2000); //-------------------------------------- setdisplay(off); clearlcdscreen(); // // select 16 colors/gray shades // if (paneld == panel_mono) { val = readregister(1); val |= 0x08; // set aux[01] bit 3 writeregister(1, val); val = readregister(3); val &= 0xf9; // clear aux[03] bits 1 and 2 writeregister(3, val); // // update lookup table for 16 gray shades //
epson research and development page 71 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, monolut16[x]); } str = gray16; } else // 16 colors { val = readregister(1); val |= 0x08; // set aux[01] bit 3 writeregister(1, val); val = readregister(3); val &= 0xfb; // clear aux[03] bit 2 val |= 0x02; // set aux[03] bit 1 writeregister(3, val); // // update lookup table for 16 colors // for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, colorlut16red[x]); writeregister(0x0f, colorlut16green[x]); writeregister(0x0f, colorlut16blue[x]); } str = color16; } // // update line byte count register for 16 colors/gray shades // // since 16 colors/gray shades corresponds to 2 pixels per byte, there // are ((x horizontal pixels)/2) bytes per scan line. this means that // there are ((x horizontal pixels)/4) words per scan line. // // since the memory interface is set to 16 bits, the line byte/word count // refers to words. // val = (panelx / 4) - 1; bytesperscanline = (panelx / 2); writeregister(2, val & 0xff); // line byte count register val2 = readregister(3); val2 &= 0xfe; // clear bit 0 val2 |= (val >> 8) & 0x01; writeregister(3, val2); // mode register 1
page 72 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 panelgraylevel = 16; showverticalbars(pvideo, 0); // // show text. the lightest color/gray shade is set to panelgraylevel-1. // showtext(pvideo, bank0, str, panelgraylevel-1); setdisplay(on); delay(2000); //-------------------------------------- if (paneld == panel_color) { setdisplay(off); clearlcdscreen(); // // select 256 colors // val = readregister(3); val |= 0x06; // set aux[03] bits 1 and 2 writeregister(3, val); // // update lookup table for 256 colors // for (x = 0; x < 16; ++x) { writeregister(0x0e, x); writeregister(0x0f, colorlut256red[x]); writeregister(0x0f, colorlut256green[x]); writeregister(0x0f, colorlut256blue[x]); } // // update line byte/word count register for 256 colors // // since 256 colors have one pixel per byte, there // are (x horizontal pixels) bytes per scan line. this means that // there are ((x horizontal pixels)/2) words per scan line. // // since the memory interface is set to 16 bits, the line byte/word count // refers to words. // val = (panelx / 2) - 1; bytesperscanline = panelx; writeregister(2, val & 0xff); // line byte count register
epson research and development page 73 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 val2 = readregister(3); val2 &= 0xfe; // clear bit 0 val2 |= (val >> 8) & 0x01; writeregister(3, val2); // mode register 1 panelgraylevel = 256; showverticalbars(pvideo, 0); // // show text. the lightest color is set to panelgraylevel-1. // showtext(pvideo, bank0, "horizontal/vertical bars at 256 colors", panelgraylevel- 1); setdisplay(on); delay(2000); } else setdisplay(on); showmenu(); } //------------------------------------------------------------------------- // // showtext() // // description: writes text to the lcd panel. text must only contain // the letters a-z, and the space character. all other // characters are replaced by spaces. // // notes: it is assumed that a pixel set to a value of 0 represents the // background color (black). // //------------------------------------------------------------------------- void showtext(unsigned char _far *pvideostart, unsigned char bank, char *str, int color) { static const unsigned char *pfont; static unsigned char _far *pvideofirstcolumn; static unsigned char _far *pvideo; static unsigned char ch; static unsigned int y, val, video; static unsigned int count; // // each letter in the font is 8 x 8 bits // #define max_font 97 static const unsigned char font[max_font][8] = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // (blank)
page 74 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 { 0x30, 0x78, 0x78, 0x30, 0x30, 0x00, 0x30, 0x00 }, // ! { 0x6c, 0x6c, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00 }, // " { 0x6c, 0x6c, 0xfe, 0x6c, 0xfe, 0x6c, 0x6c, 0x00 }, // # { 0x30, 0x7c, 0xc0, 0x78, 0x0c, 0xf8, 0x30, 0x00 }, // $ { 0x00, 0xc6, 0xcc, 0x18, 0x30, 0x66, 0xc6, 0x00 }, // % { 0x38, 0x6c, 0x38, 0x76, 0xdc, 0xcc, 0x76, 0x00 }, // & { 0x60, 0x60, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ' { 0x18, 0x30, 0x60, 0x60, 0x60, 0x30, 0x18, 0x00 }, // ( { 0x60, 0x30, 0x18, 0x18, 0x18, 0x30, 0x60, 0x00 }, // ) { 0x00, 0x66, 0x3c, 0xff, 0x3c, 0x66, 0x00, 0x00 }, // * { 0x00, 0x30, 0x30, 0xfc, 0x30, 0x30, 0x00, 0x00 }, // + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x60 }, // , { 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x00 }, // - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00 }, // . { 0x06, 0x0c, 0x18, 0x30, 0x60, 0xc0, 0x80, 0x00 }, // / { 0x7c, 0xc6, 0xce, 0xde, 0xf6, 0xe6, 0x7c, 0x00 }, // 0 { 0x30, 0x70, 0x30, 0x30, 0x30, 0x30, 0xfc, 0x00 }, // 1 { 0x78, 0xcc, 0x0c, 0x38, 0x60, 0xcc, 0xfc, 0x00 }, // 2 { 0x78, 0xcc, 0x0c, 0x38, 0x0c, 0xcc, 0x78, 0x00 }, // 3 { 0x1c, 0x3c, 0x6c, 0xcc, 0xfe, 0x0c, 0x1e, 0x00 }, // 4 { 0xfc, 0xc0, 0xf8, 0x0c, 0x0c, 0xcc, 0x78, 0x00 }, // 5 { 0x38, 0x60, 0xc0, 0xf8, 0xcc, 0xcc, 0x78, 0x00 }, // 6 { 0xfc, 0xcc, 0x0c, 0x18, 0x30, 0x30, 0x30, 0x00 }, // 7 { 0x78, 0xcc, 0xcc, 0x78, 0xcc, 0xcc, 0x78, 0x00 }, // 8 { 0x78, 0xcc, 0xcc, 0x7c, 0x0c, 0x18, 0x70, 0x00 }, // 9 { 0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x00 }, // : { 0x00, 0x30, 0x30, 0x00, 0x00, 0x30, 0x30, 0x60 }, // ; { 0x18, 0x30, 0x60, 0xc0, 0x60, 0x30, 0x18, 0x00 }, // < { 0x00, 0x00, 0xfc, 0x00, 0x00, 0xfc, 0x00, 0x00 }, // = { 0x60, 0x30, 0x18, 0x0c, 0x18, 0x30, 0x60, 0x00 }, // > { 0x78, 0xcc, 0x0c, 0x18, 0x30, 0x00, 0x30, 0x00 }, // ? { 0x7c, 0xc6, 0xde, 0xde, 0xde, 0xc0, 0x78, 0x00 }, // @ { 0x30, 0x78, 0xcc, 0xcc, 0xfc, 0xcc, 0xcc, 0x00 }, // a { 0xfc, 0x66, 0x66, 0x7c, 0x66, 0x66, 0xfc, 0x00 }, // b { 0x3c, 0x66, 0xc0, 0xc0, 0xc0, 0x66, 0x3c, 0x00 }, // c { 0xf8, 0x6c, 0x66, 0x66, 0x66, 0x6c, 0xf8, 0x00 }, // d { 0xfe, 0x62, 0x68, 0x78, 0x68, 0x62, 0xfe, 0x00 }, // e { 0xfe, 0x62, 0x68, 0x78, 0x68, 0x60, 0xf0, 0x00 }, // f { 0x3c, 0x66, 0xc0, 0xc0, 0xce, 0x66, 0x3e, 0x00 }, // g { 0xcc, 0xcc, 0xcc, 0xfc, 0xcc, 0xcc, 0xcc, 0x00 }, // h { 0x78, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00 }, // i { 0x1e, 0x0c, 0x0c, 0x0c, 0xcc, 0xcc, 0x78, 0x00 }, // j { 0xe6, 0x66, 0x6c, 0x78, 0x6c, 0x66, 0xe6, 0x00 }, // k { 0xf0, 0x60, 0x60, 0x60, 0x62, 0x66, 0xfe, 0x00 }, // l { 0xc6, 0xee, 0xfe, 0xfe, 0xd6, 0xc6, 0xc6, 0x00 }, // m { 0xc6, 0xe6, 0xf6, 0xde, 0xce, 0xc6, 0xc6, 0x00 }, // n { 0x38, 0x6c, 0xc6, 0xc6, 0xc6, 0x6c, 0x38, 0x00 }, // o { 0xfc, 0x66, 0x66, 0x7c, 0x60, 0x60, 0xf0, 0x00 }, // p { 0x78, 0xcc, 0xcc, 0xcc, 0xdc, 0x78, 0x1c, 0x00 }, // q { 0xfc, 0x66, 0x66, 0x7c, 0x6c, 0x66, 0xe6, 0x00 }, // r { 0x78, 0xcc, 0xe0, 0x70, 0x1c, 0xcc, 0x78, 0x00 }, // s { 0xfc, 0xb4, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00 }, // t { 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xfc, 0x00 }, // u
epson research and development page 75 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 { 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x00 }, // v { 0xc6, 0xc6, 0xc6, 0xd6, 0xfe, 0xee, 0xc6, 0x00 }, // w { 0xc6, 0xc6, 0x6c, 0x38, 0x38, 0x6c, 0xc6, 0x00 }, // x { 0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x30, 0x78, 0x00 }, // y { 0xfe, 0xc6, 0x8c, 0x18, 0x32, 0x66, 0xfe, 0x00 }, // z { 0x78, 0x60, 0x60, 0x60, 0x60, 0x60, 0x78, 0x00 }, // [ { 0xc0, 0x60, 0x30, 0x18, 0x0c, 0x06, 0x02, 0x00 }, // (backslash) { 0x78, 0x18, 0x18, 0x18, 0x18, 0x18, 0x78, 0x00 }, // ] { 0x10, 0x38, 0x6c, 0xc6, 0x00, 0x00, 0x00, 0x00 }, // ^ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff }, // _ { 0x30, 0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ? { 0x00, 0x00, 0x78, 0x0c, 0x7c, 0xcc, 0x76, 0x00 }, // a { 0xe0, 0x60, 0x60, 0x7c, 0x66, 0x66, 0xdc, 0x00 }, // b { 0x00, 0x00, 0x78, 0xcc, 0xc0, 0xcc, 0x78, 0x00 }, // c { 0x1c, 0x0c, 0x0c, 0x7c, 0xcc, 0xcc, 0x76, 0x00 }, // d { 0x00, 0x00, 0x78, 0xcc, 0xfc, 0xc0, 0x78, 0x00 }, // e { 0x38, 0x6c, 0x60, 0xf0, 0x60, 0x60, 0xf0, 0x00 }, // f { 0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8 }, // g { 0xe0, 0x60, 0x6c, 0x76, 0x66, 0x66, 0xe6, 0x00 }, // h { 0x30, 0x00, 0x70, 0x30, 0x30, 0x30, 0x78, 0x00 }, // i { 0x0c, 0x00, 0x0c, 0x0c, 0x0c, 0xcc, 0xcc, 0x78 }, // j { 0xe0, 0x60, 0x66, 0x6c, 0x78, 0x6c, 0xe6, 0x00 }, // k { 0x70, 0x30, 0x30, 0x30, 0x30, 0x30, 0x78, 0x00 }, // l { 0x00, 0x00, 0xcc, 0xfe, 0xfe, 0xd6, 0xc6, 0x00 }, // m { 0x00, 0x00, 0xf8, 0xcc, 0xcc, 0xcc, 0xcc, 0x00 }, // n { 0x00, 0x00, 0x78, 0xcc, 0xcc, 0xcc, 0x78, 0x00 }, // o { 0x00, 0x00, 0xdc, 0x66, 0x66, 0x7c, 0x60, 0xf0 }, // p { 0x00, 0x00, 0x76, 0xcc, 0xcc, 0x7c, 0x0c, 0x1e }, // q { 0x00, 0x00, 0xdc, 0x76, 0x66, 0x60, 0xf0, 0x00 }, // r { 0x00, 0x00, 0x7c, 0xc0, 0x78, 0x0c, 0xf8, 0x00 }, // s { 0x10, 0x30, 0x7c, 0x30, 0x30, 0x34, 0x18, 0x00 }, // t { 0x00, 0x00, 0xcc, 0xcc, 0xcc, 0xcc, 0x76, 0x00 }, // u { 0x00, 0x00, 0xcc, 0xcc, 0xcc, 0x78, 0x30, 0x00 }, // v { 0x00, 0x00, 0xc6, 0xd6, 0xfe, 0xfe, 0x6c, 0x00 }, // w { 0x00, 0x00, 0xc6, 0x6c, 0x38, 0x6c, 0xc6, 0x00 }, // x { 0x00, 0x00, 0xcc, 0xcc, 0xcc, 0x7c, 0x0c, 0xf8 }, // y { 0x00, 0x00, 0xfc, 0x98, 0x30, 0x64, 0xfc, 0x00 }, // z { 0x1c, 0x30, 0x30, 0xe0, 0x30, 0x30, 0x1c, 0x00 }, // { { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00 }, // | { 0xe0, 0x30, 0x30, 0x1c, 0x30, 0x30, 0xe0, 0x00 }, // } { 0x76, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // ~ { 0x00, 0x10, 0x38, 0x6c, 0xc6, 0xc6, 0xfe, 0x00 }, // 127 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } }; // block char pvideofirstcolumn = pvideostart; pvideo = pvideofirstcolumn; // // select memory bank by reading or writing to port. // if (bank == 1) outp(panelportaddr+2, 0);
page 76 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 else inp(panelportaddr+2); switch (panelgraylevel) { case 2: // // if there are 2 gray levels, there are 8 pixels/byte // color &= 0x01; while (*str != 0) { ch = *str++; if ((ch < ' ') || (ch - ' ' > max_font-1)) ch = '.'; pfont = &font[ch - ' '][0]; for (y = 0; y < 8; ++y) { pvideo = pvideofirstcolumn; video = 0; val = *pfont++; // // since there are 2 gray shades, each bit in the font will be // represented in video memory as a one bit pixel. // if (val & 0x80) video |= (color << 7); if (val & 0x40) video |= (color << 6); if (val & 0x20) video |= (color << 5); if (val & 0x10) video |= (color << 4); if (val & 0x08) video |= (color << 3); if (val & 0x04) video |= (color << 2); if (val & 0x02) video |= (color << 1); if (val & 0x01)
epson research and development page 77 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); pvideofirstcolumn += bytesperscanline; } ++pvideostart; // point to next character pvideofirstcolumn = pvideostart; } break; case 4: // // if there are 4 colors/gray levels, there are 4 pixels/byte // color &= 0x03; while (*str != 0) { ch = *str++; if ((ch < ' ') || (ch - ' ' > max_font-1)) ch = '.'; pfont = &font[ch - ' '][0]; for (y = 0; y < 8; ++y) { pvideo = pvideofirstcolumn; video = 0; val = *pfont++; // // since there are 4 colors/gray shades, each bit in the font will be // represented in video memory as a two bit pixel. // if (val & 0x80) video |= (color << 6); if (val & 0x40) video |= (color << 4); if (val & 0x20) video |= (color << 2); if (val & 0x10) video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank);
page 78 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 video = 0; if (val & 0x08) video |= (color << 6); if (val & 0x04) video |= (color << 4); if (val & 0x02) video |= (color << 2); if (val & 0x01) video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); pvideofirstcolumn += bytesperscanline; } pvideostart += 2; // point to next character pvideofirstcolumn = pvideostart; } break; case 16: color &= 0x0f; while (*str != 0) { ch = *str++; if ((ch < ' ') || (ch - ' ' > max_font-1)) ch = '.'; pfont = &font[ch - ' '][0]; for (y = 0; y < 8; ++y) { pvideo = pvideofirstcolumn; video = 0; val = *pfont++; // // since there are 16 colors/gray shades, each bit in the font will be // represented in video memory as a four bit pixel. // if (val & 0x80) video |= (color << 4); if (val & 0x40) video |= color;
epson research and development page 79 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); video = 0; if (val & 0x20) video |= (color << 4); if (val & 0x10) video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); video = 0; if (val & 0x08) video |= (color << 4); if (val & 0x04) video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); video = 0; if (val & 0x02) video |= (color << 4); if (val & 0x01) video |= color; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); pvideofirstcolumn += bytesperscanline; } pvideostart += 4; // point to next character pvideofirstcolumn = pvideostart; } break; case 256: while (*str != 0) { ch = *str++; if ((ch < ' ') || (ch - ' ' > max_font-1)) ch = '.'; pfont = &font[ch - ' '][0]; for (y = 0; y < 8; ++y)
page 80 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 { pvideo = pvideofirstcolumn; video = 0; val = *pfont++; // // since there are 256 colors, each bit in the font will be // represented in video memory as an 8 bit pixel. // for (count = 0; count < 8; ++count) { if (val & 0x80) video = color; else video = 0; *pvideo++ = (unsigned char) video; checkbank(pvideo, &bank); val <<= 1; } pvideofirstcolumn += bytesperscanline; } pvideostart += 8; // point to next character pvideofirstcolumn = pvideostart; } break; } } //------------------------------------------------------------------------- // // function: splitscreen() // // description: show split screen. // // inputs: none. // return value: none. // //------------------------------------------------------------------------- void splitscreen(void) { static unsigned char _far *pvideoimage1; static unsigned char _far *pvideoimage2; static unsigned long imagesize; static unsigned int originallinecount; static unsigned int val; static int minlinecount; static unsigned int maxvirtualscanlines; static unsigned char image2bank;
epson research and development page 81 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 printf("showing split screen\n"); initialize(); setdisplay(off); clearlcdscreen(); // // access memory banks // fp_seg(pvideoimage1) = 0xd000; fp_off(pvideoimage1) = 0x0000; switch (panelgraylevel) { case 2: bytesperscanline = (panelx / 8); break; case 4: bytesperscanline = (panelx / 4); break; case 16: bytesperscanline = (panelx / 2); break; case 256: bytesperscanline = panelx; break; } showverticalbars(pvideoimage1, 0); // // calculate starting video memory location for image 2 by finding the // last location of image 1 // imagesize = (unsigned long) bytesperscanline * panely; // // because the image size is limited to a maximum of 320 x 240, and there // is 128k of video memory, there is enough memory available. // fp_seg(pvideoimage2) = 0xd000; fp_off(pvideoimage2) = (unsigned int) (imagesize & 0xffff); if (imagesize & 0xffff0000) image2bank = bank1;
page 82 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 else image2bank = bank0; showhorizontalbars(pvideoimage2, image2bank); // // show text. the lightest color/gray shade is set to panelgraylevel-1. // showtext(pvideoimage1, bank0, "split screen image one", panelgraylevel-1); showtext(pvideoimage2, image2bank, "split screen image two", panelgraylevel-1); // // set screen 2 display start address register to point to image 2 // // adjust imagesize to represent the size in words, not bytes. // this is because the memory interface is set to 16 bits. // val = (unsigned int) (imagesize / 2); writeregister(8, (unsigned int) val & 0xff); writeregister(9, (unsigned int) val >> 8); setdisplay(on); // // if this is a dual panel, then the split screen has just been shown. // otherwise, set up the screen 1 display line count register for single // panels. // if (paneltype == type_single) { originallinecount = (unsigned int) ((readregister(0x0b) & 0x03) << 8) | readregister(0x0a); // only for 128k of memory maxvirtualscanlines = (unsigned int) ((unsigned long) 0x20000 / bytesperscanline); minlinecount = originallinecount - (maxvirtualscanlines - originallinecount) + 1; if (minlinecount < 0) minlinecount = 0; // // scroll image 2 down // for (val = minlinecount; val < originallinecount; val += 1)
epson research and development page 83 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 { writeregister(0x0a, val & 0xff); // total display line count writeregister(0x0b, (val >> 8) & 0x03); // total disp line cnt/wf count delay(delay_short); } // // scroll image 2 up // for (val = originallinecount; val > (unsigned int) minlinecount; val -= 1) { writeregister(0x0a, val & 0xff); // total display line count writeregister(0x0b, (val >> 8) & 0x03); // total disp line cnt/wf count delay(delay_short); } val = minlinecount; writeregister(0x0a, val & 0xff); // total display line count reg writeregister(0x0b, (val >> 8) & 0x03); // total disp line cnt/wf count delay(500); } showmenu(); } void setstartaddress(int x, int y) { int addr; switch (panelgraylevel) { case 16: addr = (unsigned int) ((x/2 + (virtual_x/2) * y)/2); break; case 256: addr = (unsigned int) ((x + virtual_x * y)/2); break; } writeregister(6, addr & 0xff); writeregister(7, addr >> 8); } void panscroll(void) { static unsigned int x, y;
page 84 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 static unsigned int maxx, maxy; static unsigned int val, pitch; static unsigned char _far *pvideo; static unsigned char bank, color; printf("showing panning and scrolling\n"); initialize(); setdisplay(off); clearlcdscreen(); switch (panelgraylevel) { case 16: pitch = (unsigned int) (((virtual_x / 2) - bytesperscanline) / 2); bytesperscanline = (virtual_x / 2); break; case 256: pitch = (unsigned int) ((virtual_x - bytesperscanline) / 2); bytesperscanline = virtual_x; break; } writeregister(0x0d, pitch); // // access memory banks // fp_seg(pvideo) = 0xd000; fp_off(pvideo) = 0x0000; // // display random blocks of data. to do so, a text character will be used. // this character sets all pixels in a character region, so a block is // shown at the specified gray shade. // // seed the random number generator with current time srand((unsigned) time(null)); for (x = 0; x < 300; ++x) { if (((rand() * 2l) / rand_max) == 1) bank = bank0; else bank = bank1;
epson research and development page 85 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 fp_off(pvideo) = (unsigned int) ((rand() * 0xffffl) / rand_max); val = rand() % 50; switch (panelgraylevel) { case 16: color = (unsigned char) (rand() % 16); break; case 256: color = (unsigned char) (rand() % 256); break; } // the last character in the font table is a solid block character. showtext(pvideo, bank, "\x80", color); } showborders(); // // move virtual display from (0, 0) to (maxx, 0) // maxx = (unsigned int) (virtual_x - panelx); maxy = (unsigned int) (virtual_y - panely); setdisplay(on); for (x = 0; x <= maxx; ++x) { setstartaddress(x, 0); delay(delay_short); } for (y = 0; y <= maxy; ++y) { setstartaddress(maxx, y); delay(delay_short); } for (x = maxx; x > 0; --x) { setstartaddress(x, maxy); delay(delay_short); } for (y = maxy; y > 0; --y) { setstartaddress(0, y); delay(delay_short); } setstartaddress(0, 0);
page 86 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 showmenu(); } //------------------------------------------------------------------------- // // function: powersaving() // // description: starts power saving mode 2. // // inputs: none. // return value: none. // //------------------------------------------------------------------------- void powersaving(void) { static unsigned int val; printf("starting power saving\n"); // // the following are the steps to enter a power save mode. // // // step 1: turn off display // val = readregister(1); val &= 0x7f; writeregister(1, val); // // step 2: disable lcde (turn off lcd power supply). // for the s5u13503b00c, set lcde bit to 0. // val = readregister(1); val &= 0xef; writeregister(1, val); // // step 2: wait for lcd power supply to drop to zero volts // for the s5u13503b00c, wait about a half second. // delay(500); // // step 3: enter power save mode // val = readregister(3); val &= 0x3f; val |= 0x80; writeregister(3, val); // set power saving mode 2
epson research and development page 87 vancouver design center programming notes and examples s1d13503 issue date: 01/01/30 x18a-g-002-06 printf("press any key to cancel power saving\n"); getch(); // // the following are the steps to exit a power save mode. // // // step 1: exit power save mode // val = readregister(3); val &= 0x3f; writeregister(3, val); // cancel power saving mode 2 // // step 2: enable lcde (turn on lcd power supply). // for the s5u13503b00c, set lcde bit to 1. // val = readregister(1); val |= 0x10; writeregister(1, val); // // step 3: turn on display. // val = readregister(1); val |= 0x80; writeregister(1, val); showmenu(); }
page 88 epson research and development vancouver design center s1d13503 programming notes and examples x18a-g-002-06 issue date: 01/01/30 8 glossary 13503 the s1d13503 lcd controller chip. bank in reference to display memory banking, a bank is a 64k byte block of display memory. bank 0 represents the first 64k bytes of display memory, and bank 1 represents the second 64k bytes. color a specific combination of red, green, and blue intensities. display memory memory in which an image is stored for display by the s1d13503. gray shade a specific combination of white and black colors. for example, a lighter gray shade has more white than black. lcd liquid crystal display. the display device used by the s1d13503. lcd controller the device used to control the lcd display. the s1d13503 is an lcd controller. lut look-up table, or palette. the lut treats the value of a pixel as an index into an array of colors or gray shades. panel the circuitry and viewable area of an lcd display which supports a single image. lcd displays may have one or two panels. panning the right or left movement of the viewport in a virtual display. pixel picture element. a pixel is seen as a dot on the display, and can be shown using one of several different colors or gray shades. combining pixels in a group creates an image. power saving a means of reducing the power consumption of the s1d13503. register a memory storage location to control a peripheral, such as the s1d13503. scrolling the up and down movement of the viewport in a virtual display. s1d13503 the 13503 chip. s5u13503b00c the evaluation board for the s1d13503. the s5u13503b00c is an isa board for a pc- compatible computer. viewport the visible portion of a virtual display. virtual display an image, which is stored in display memory, that is larger than what the lcd display can show. a virtual display supports panning and scrolling.
s1d13503f00a register summary x18a-q-002-05 page 1 01/03/02 aux[00] t e s t r e g i s t e r : i/o address = 0000b, rw test mode enable reserved must = 0 test input select / scratch test output select / scratch bit 2 bit 1 bit 0 bit 2 bit 1 bit 0 aux[01] m o d e r e g i s t e r 0: i/o address = 0001b, rw disp panel mask xscl lcde gray shade / color lcd data width bit 0 memory interface rams aux[02] l i n e b y t e c o u n t r e g i s t e r (lsb): i/o address = 0010b, rw line byte count (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[03] m o d e r e g i s t e r 1: i/o address = 0011b, rw power save mode lcd signal state lut bypass lcd data width bit 1 bw / 256 colors color mode line byte count bit 8 bit 1 bit 0 aux[04] t o t a l d i s p l a y l i n e c o u n t r e g i s t e r (lsb): i/o address = 0100b, rw total display line count (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[05] t o t a l d i s p l a y l i n e c o u n t r e g i s t e r (msb) a n d wf c o u n t r e g i s t e r : i/o address = 0101b, rw wf count total display line count bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 9 bit 8 aux[06] s c r e e n 1 d i s p l a y s t a r t a d d r e s s r e g i s t e r (lsb): i/o address = 0110b, rw screen 1 display start address (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[07] s c r e e n 1 d i s p l a y s t a r t a d d r e s s r e g i s t e r (msb): i/o address = 0111b, rw screen 1 display start address (high byte) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 aux[08] s c r e e n 2 d i s p l a y s t a r t a d d r e s s r e g i s t e r (lsb): i/o address = 1000b, rw screen 2 display start address (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[09] s c r e e n 2 d i s p l a y s t a r t a d d r e s s r e g i s t e r (msb): i/o address = 1001b, rw screen 2 display start address (high byte) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 aux[0a] s c r e e n 1 d i s p l a y l i n e c o u n t r e g i s t e r (lsb): i/o address = 1010b, rw screen 1 display line count (low byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[0b] s creen 1 d isplay l ine c ount r egister (msb): i/o address = 1011b, rw n/a 1 n/a n/a n/a n/a n/a screen 1 disp line count bit 9 bit 8 aux[0c] h orizontal n on -d isplay p eriod r egister : i/o address = 1100b, rw horizontal non-display period bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[0d] a ddress p itch a djustment r egister : i/o address = 1101b, rw address pitch adjustment bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aux[0e] l ook -u p t able a ddress r egister : i/o address = 1110b, rw green bank select id 2 / rgb index palette address bit 1 bit 0 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 aux[0f] l ookup t able d ata r egister : i/o address = 1111b, rw red bank select blue bank select palette data bit 1 bit 0 bit 1 bit 0 bit 3 bit 2 bit 1 bit 0 notes 1 n/a bits should be written 0. 2 these bits are used to identify the s1d13503 at power on / reset. if these bits read 00b at power on / reset the device is an s1d13503f00a. if this bit reads 10b at power on / reset the device is an s1d13502f00b. if this bit reads 11b at power on / reset the device is an s1d13502f00a. s1d13503f00a register summary
s1d13503f00a register summary x18a-q-002-05 page 2 01/03/02
s1d13503 dot matrix graphics lcd controller 13503show.exe display utility document number: x18a-b-001-05 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503show.exe display utility s1d13503 issue date: 01/01/29 x18a-b-001-05 13503show.exe display utility 13503show is a utility used to load and display gif images. it can also be used to demonstrate the split screen capabilities of the s1d13503 by loading two images and vertically scrolling one image. program requirements installation copy the file 13503show.exe to a directory that is in the dos path on your hard drive. usage 13503show is invoked from the dos command line as follows: 13503show [file1.gif] [file2.gif] [/i] [/k] [/v] [/?] where : file1.gif is the first screen image to be displayed. file2.gif is the second screen image to be displayed. /i inverts all displayed images (show as negative) - used for some monochrome panels (works in monochrome mode only). /k exit the program and keep the image on the display - useful in batch file execution such as demonstrations. /v verbose mode - useful to determine gif information if it is not known. /d leave the display on while loading image - useful for animation. /? produces the usage message. video controller : s1d13503 display type : up to 640x480 lcd bios : seiko epson 13503bios version 1.xx or later dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503show.exe display utility x18a-b-001-05 issue date: 01/01/29 examples: 13503show with no arguments will run the program in split screen mode. this will display two predefined images, with screen one displaying horizontal bars and screen two displaying vertical bars. screen two may be scrolled up and down using the arrow, page up, page down, home and end keys. 13503show file.gif displays the named gif image. 13503show file1.gif file2.gif displays the two named gif images in a split screen. screen two may be scrolled up and down using the arrow, page up, page down, home and end keys. pressing the esc key will terminate the program. comments 13503show requires 13503bios.com to be loaded prior to running. split screen viewing is limited on dual panels. the view port is fixed in place at the top left of the bottom lcd panel. panning and scrolling is still possible within the screen 2 view port. the size of screen two is determined by available memory and number of colors/gray shades. if there is insufficient memory for screen two 13503show will not accept the two image files and will generate an error message. when loading two gif images, it may take several seconds of apparent inactivity to load the second image into memory. the gif format must be 2, 16 or 256 color, non-interlaced gif89a format. 13503show will clear the screen when the esc key is pressed unless the /k switch is used in the command line. the file is loaded into the program at its image color depth (i.e., a 256 color image is initially displayed in 256 color mode, a 16 color image is initially displayed in 16 color mode). program messages error: this program requires bios13503 to be loaded! the program 13503bios.com must be run before 13503show. load 13503bios.com and re-run 13503show.exe. file ? filename ? not found or cannot be opened for reading. the gif file you are trying to display is not in your dos path or not on your system. file is not gif89a format. the gif file contains an invalid format. 1350313503show only supports gif89a format. insufficient video memory for second image. there is not enough video memory available to store both images.
s1d13503 dot matrix graphics lcd controller 13503virt.exe display utility document number: x18a-b-002-05 copyright ? 2001epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503virt.exe display utility s1d13503 issue date: 01/01/29 x18a-b-002-05 13503virt.exe display utility 13503virt.exe demonstrates the virtual panning capabilities of the s1d13503. two images larger than the display resolution are loaded in display memory. 13503virt.exe will then display, in a split screen, a portion of each complete image while providing panning capabilities using the arrow keys for navigation. program requirements installation copy the file 13503virt.exe to a directory that is in the dos path on your hard drive. usage 13503virt is invoked from the dos command line as follows: 13503virt g=n [/a] [/k] [/?] where : g is the number of gray shades/colors: 2 , 4 , 16 or 256 . /a automatically pan and scroll the image - useful for demonstrations. /k exit the program and keep the image on the display - useful in batch file execution for demonstrations. /? produces a usage message. the program draws a test pattern of two images on the display. the user can navigate throughout either image using the numeric keypad. use the arrow keys to pan and scroll the screen, home to go to the top left, pg up to go to the top right, end to go to the bottom left, pg dn to go to the bottom right, and 5 to go to the center of the image. pressing ctrl while using an arrow key steps the scroll or pan in smaller increments. press the num lock key to allow navigation in the second image. holding down the shift key while pressing either the up or down arrow will move the split up or down. pressing the esc key terminates the program. video controller : s1d13503 display type : up to 640x480 lcd bios : seiko epson 13503bios version 1.xx or later dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503virt.exe display utility x18a-b-002-05 issue date: 01/01/29 comments 13503virt requires 13503bios.com to be loaded prior to running. program messages error: this program requires 13503bios to be loaded! the program 13503bios.com must be run before 13503virt.exe. load 13503bios.com and then re-run 13503virt.exe.
s1d13503 dot matrix graphics lcd controller 13503bios.com utility document number: x18a-b-003-05 copyright ? 1995, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503bios.com utility s1d13503 issue date: 01/01/29 x18a-b-003-05 13503bios.com utility 13503bios is a terminate and stay resident (tsr) program which replaces and/or supplements the pc video interrupt int 10h. this program provides text, scroll, and cursor functionality when no vga bios is present. although the s1d13503 is not a vga or ega compatible controller, this program is supplied to give the user a familiar prompt. within limits 13503bios simulates a vga bios and will allow standard output functions to work. dos programs such as edlin, format, debug, and internal commands such as copy, ren, mkdir, etc., should work. however, complex programs such as edit, qbasic, and scandisk will not work. the standard output functions are handled by the vga bios, if present. program requirements installation copy the files 13503bios.com and 13503bios.ini to a directory that is in the dos path on your hard drive. usage 13503bios.com is run from the dos command line. the file 13503bios.ini is the initialization file for 13503bios.com and must reside in the same directory as 13503bios.com. this file contains the default run parameters for 13503bios.com. these parameters may be changed within the initialization file or for one time usage on the command line as follows: 13503bios d=n g=n i=n m=n p=n x=n y=n [/?] [f=n] where: d is panel type: color or mono g is the number of colors/gray shades: 2 , 4 , 16 or 256 i is the panel interface data width: 4 , 8 or 16 bits m is the memory size in k bytes: 64 or 128 p is the port address in hex: 300 | 310 ... 360 | 370 x is the horizontal panel size in pixels (decimal) y is the vertical panel size in lines (decimal) f is the 8-bit color panel format: 1 or 2 ? produces a usage message video controller : s1d13503 display type : up to 640x480 lcd bios : none or any vga dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503bios.com utility x18a-b-003-05 issue date: 01/01/29 note that the port address must be the same as the physical address set on the s5d13503 evaluation board. example: 13503bios d=color g=256 i=8 m=128 p=310 t=single x=320 y=240 f=2 comments 13503bios can be used in conjunction with a monochrome display adapter (mono) card. the standard dos command mode mono will switch to the monochrome card and the dos command mode co80 will switch to the lcd panel. 13503bios emulates mode 3, but any program that attempts to write directly to video memory, bypassing the video bios, will not display correctly. 13503bios can be used in conjunction with a vga bios. in this case all tty output will be displayed on the vga monitor. when the s1d13503 video memory is specified as 64k bytes, the s1d13503 video memory will reside at d000h to dfffh. for 128k bytes of s1d13503 video memory, the memory will reside at c000h to dfffh. program messages error: panels greater than 640 pixels not supported. more than 640 horizontal pixels has been specified for the panel in the command line. error: panels greater than 480 lines not supported. more than 480 vertical lines has been specified for the panel in the command line. error: invalid port specified. the port address ( p ) must be specified in the format 3x0 in the command line. the range is 300h to 370h in 10h increments. error: not enough memory for panel. the panel specified is too large to run in 16 gray shades mode. select 4 gray shades instead. error: video memory and vga bios memory conflict. both the s1d13503 video memory and the vga bios are trying to use the memory at location c000h to cfffh. error: only 64k or 128k memory allowed. an invalid value has been specified for memory size ( m ) on the command line.
s1d13503 dot matrix graphics lcd controller 13503mode.exe display utility document number: x18a-b-004-05 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503mode.exe display utility s1d13503 issue date: 01/01/29 x18a-b-004-05 13503mode.exe display utility 13503mode is a menu driven display utility for the s1d13503 which demonstrates the color /gray shades as well as available palettes. for 128k bytes of display memory either 4, 16 or 256 colors/gray shades are available. program requirements installation copy the file 13503mode.exe to a directory that is in the dos path on your hard drive. usage 13503mode is invoked from the dos command line as follows: 13503mode g=n [/?] [/d] [/k] where : g is the number of colors /gray shades: 2 , 4 , 16 or 256 / ? produces a usage message. /d inhibits display writes on startup - useful for examaning the l.u.t. of a previously loaded image. /k exit the program and keep the image on the display - useful for batch file execution for demonstrations. 13503mode displays a default color/gray shade pattern as a series of vertical or horizontal bars. the pattern, number of colors/gray shades and current palette may be modified by the user when possible. instructions to modify these options appear when available. an image other than the default one may be used as follows: 1. run 13503bios.com if it is not already loaded 2. load an image into the video buffer with 13503show.exe 13503show file.gif /k 3. load 13503mode /d the look-up table (l.u.t.) of the image file displayed may now be manipulated by the user. pressing the esc key terminates the program and restores the original 13503bios settings. video controller : s1d13503 display type : up to 640x480 lcd bios : seiko epson 13503bios version 1.x or later dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503mode.exe display utility x18a-b-004-05 issue date: 01/01/29 comments 13503mode requires 13503bios.com to be loaded prior to running. program messages error: this program requires 13503bios to be loaded! the program 13503bios.com must be run before 13503mode. load 13503bios.com and then re-run 13503mode.exe.
s1d13503 dot matrix graphics lcd controller 13503pd.exe power down utility document number: x18a-b-005-05 copyright ? 1996, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503pd.exe power down utility s1d13503 issue date: 01/01/29 x18a-b-005-05 13503pd.exe power down utility 13503pd is an oem utility program for setting power down modes in the s1d13503 lcd display controller that supports the sollex super vga standard video bios extensions. it provides a simple method for setting power modes during power consumption testing. program requirements installation copy the file 13503pd.exe to a directory that is in the dos path on your hard drive. usage 13503pd is run from the dos command line as follows: 13503pd modenumber where: modenumber is a decimal number (0, 1, or 2) for the desired power down mode. example : typing the following command line activates power down mode 2: 13503pd 2 output from the program can be redirected to an external dos device such as a terminal attached to the serial port such as com1 as shown below: 13503pd 2 > com1 striking any key will set mode state 0 (no power down). video controller : s1d13503 display type : up to 640x480 lcd bios : seiko epson 13503bios version 1.xx or later dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503pd.exe power down utility x18a-b-005-05 issue date: 01/01/29 comments 13503pd.exe requires 13503bios.com to be loaded prior to running. the following power modes are supported: mode 0 mode 0 operates at full power. mode 1 or 2 s1d13503 will engage power down mode 1 or 2. the s1d13503 look-up table will be disabled and all lcd signals are forced low. program messages power down mode xx is set. the power down mode xx has been set. this message may not be visible if the active display controller is the s1d13503. error: cannot set power mode xx! 13503pd.exe cannot set the power down mode requested - either 13503bios.com is not loaded or the power down mode number exceeds 2. error: this program requires 13503bios to be loaded! the program 13503bios.com must be run before 13503pd. load 13503bios and re-run 13503pd.exe.
s1d13503 dot matrix graphics lcd controller 13503read.exe diagnostic utility document number: x18a-b-006-05 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center 13503read.exe diagnostic utility s1d13503 issue date: 01/01/29 x18a-b-006-05 13503read.exe diagnostic utility 13503read is an oem utility program which enables the user to read the s1d13503 register contents. it is a useful utility for oems wishing to submit a problem report for the video controller. if run with 13503bios loaded, it will try to interpret the bios settings. program requirements note 13503read uses ? stdout ? calls and may be redirected to a file or piped to a dos filter such as more.com. installation copy the file 13503read.exe to a directory that is in the dos path on your hard drive. usage from dos prompt, type the following: 13503read [p=n] [/?] where: 13503read without any argument will read the s1d13503 registers, including the palettes. p is the s1d13503 port address in hex (e.g. 310). /? produces a usage message. example: to generate a report, simply type 13503read [port] > report.txt and the information which 13503read obtains will be stored in the file report.txt. video controller : s1d13503 display type : up to 640x480 lcd bios : seiko epson 13503bios.com (optional) dos program : yes dos version : 3.0 or greater windows program : no windows dos box : yes windows dos full screen : yes os/2 dos full screen : yes
page 4 epson research and development vancouver design center s1d13503 13503read.exe diagnostic utility x18a-b-006-05 issue date: 01/01/29 comments it is not necessary to specify a port address if 13503bios has previously been loaded. 13503read will search for 13503bios.com. if this program is found the port address reported by 13503bios will be used. if the port address is specified on the 13503read command line the two port addresses are compared and if different an error message is generated. 13503read will accept any port address, however, the s5u13503 can only be configured to an address in the range of 300h through 370h. program messages error: 13503 registers not responding at port address [port]. 13503read has not found an s1d13503 at the port address specified. check the command line port setting for 13503bios and/or 13503read to ensure it is correct and re-run the program. error: 13503read requires a port address. 13503read has not detected 13503bios.com to obtain the port address and no port address was specified on the command line. either specify a port address on the 13503read command line or run 13503bios.com prior to running 13503read. error: 13503bios reports a port address of [port], which is different from the specified port address of [port]. the port address entered for 13503read is different than the one entered for 13503bios.com. specify the same port address on the 13503read command line as the one in 13503bios.com and the physical address of the s5u13503 evaluation board and re-run the program. warning: 13503bios state is out of sync with s1d13503 registers. one or more of the following command line items reported by 13503bios does not match the values found in the s1d13503 registers; horizontal panel size, vertical panel size, number of colors/gray shades, or panel type (single or dual).
s1d13503 dot matrix graphics lcd controller s5u13503b00c rev. 1.0 evaluation board user manual document number: x18a-g-007-05 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 table of contents 1 s5u13503b00c rev 1.0 evaluation board . . . . . . . . . . . . . . . . . . .7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 installation and configuration . . . . . . . . . . . . . . . . . . . . . . . .8 3 technical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 isa bus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 non-isa bus support . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 sram support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 monochrome lcd support . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 color lcd support . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 adjustable lcd panel negative power supply . . . . . . . . . . . . . . . . 15 3.8 adjustable lcd panel positive power supply . . . . . . . . . . . . . . . . 15 3.9 crystal support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 oscillator support . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 cpu/bus interface header strips . . . . . . . . . . . . . . . . . . . . . 16 3.12 schematic notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 appendix a parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 appendix b s5u13503b00c rev. 1.0 schematic diagrams . . . . . . . . . . . . 18
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epson research and development page 5 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 list of tables table 2-1: configuration dip switch settings . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 2-2: i/o mapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2-3: decoding jumper setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2-4: lcd signal connector j1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 2-5: cpu/bus connector h1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2-6: cpu/bus connector h2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 list of figures figure 1: s5u13503b00c rev. 1.0 schematic diagram (1 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 2: s5u13503b00c rev. 1.0 schematic diagram (2 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3: s5u13503b00c rev. 1.0 schematic diagram (3 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4: s5u13503b00c rev. 1.0 schematic diagram (4 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 5: s5u13503b00c rev. 1.0 schematic diagram (5 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6: s5u13503b00c rev. 1.0 schematic diagram (6 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 7: s5u13503b00c rev. 1.0 schematic diagram (7 of 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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epson research and development page 7 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 1 s5u13503b00c rev 1.0 evaluation board this manual reflects the use of the s5u13503b00c rev 1.0 evaluation board in conjunction with the s1d13503 lcd controller. all appropriate components are surface-mount to reduce cost and minimize board space. 1.1 features 100 pin qfp5 package smd technology for all appropriate devices 4/8-bit monochrome stn lcd display support 4/8/16-bit color stn lcd display support 8/16-bit isa bus support 5v operation two terminal crystal support (up to 25.0mhz) oscillator support 16-bit wide, 128k bytes sram support configuration options support for software power save modes on-board adjustable lcd bias negative power supply on-board adjustable lcd bias positive power supply cpu/bus interface header strips for non-isa bus support
page 8 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 2 installation and configuration the s1d13503 uses the display memory data lines (vd[15:0]) as configuration inputs which are read on power-up. for the purpose of this design, most of these configuration inputs have been factory set and therefore are not configurable. an eight position dip switch is provided for the selection of the following: note the polarity of the configuration dip switches is closed = ? 1 ? or ? high ? , open = ? 0 ? or ? low ? . note vd[15:0] have internal pull-down resistors and therefore external pull-up resistors are only required if the configuration option requires a ? 1 ? state on power-up. factory set fixed options on this board are: 16-bit display memory interface. all 128k bytes of video memory is available at memory segment $d with software selecting one of two 64k memory banks (see ? sram support ? on page 14). this board is pre-set to use indexed i/o with address $03y0 (0000 0011 0yyy 000x), where x is don ? t care and yyy can be configured with dip-switch sw1-5 through sw1-7. the factory setting of yyy = 001, i.e., i/o address = $0310 and $0311. direct-mapping i/o is only available for non-isa bus support. when using direct-mapped i/o, the i/o address is $03yx (0000 0011 0yyy xxxx), where x is don ? t care and yyy can be configured with dip-switch sw1-5 through sw1-7. if yyy = 001, then the i/o address for aux[00] = $0310, i/o address for aux[01] = $0311, i/o address for aux[02] = $0312 and so on. (see non-isa bus support, on page 14.) table 2-1: configuration dip switch settings switch signal closed open sw1-1 vd0 16-bit isa bus interface 8-bit isa bus interface sw1-2 vd1 direct-mapping i/o indexed i/o sw1-3 vd2 m68k cpu interface isa bus interface sw1-4 vd3 byte-swap high and low data bytes no byte-swap sw1-5 vd7 i/o mapping address bit 4 see table 2-2, ? i/o mapping example ? sw1-6 vd8 i/o mapping address bit 5 sw1-7 vd9 i/o mapping address bit 6 sw1-8 - reserved reserved table 2-2: i/o mapping example bit 6bit 5bit 4 i/o mapping address (hex) 0 0 1
epson research and development page 9 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 note these jumpers are necessary for the external isa bus decode logic. hard-wired configuration inputs for isa bus support options, external 10k ohm pull-up resistors have been assembled, and are connected to signal lines vd11, vd12, vd14 and vd15 (r6, r5, r4 and r3 respectively). for non-isa bus support (see page 14), the following signal lines may require the 10k ohm pull-up resistors installed: vd4 (r18), vd5 (r19), vd6 (r20), vd10 (r21) and/or vd13 (r17) see the s1d13503 hardware functional specification, x18a-a-001-xx, page 21 for configuration details. table 2-3: decoding jumper setting description 1-2 2-3 jp1 set to the same polarity as sw1-1 (vd0) 1 0 jp2 set to the same polarity as sw1-5 (vd7) 1 0 jp3 set to the same polarity as sw1-6 (vd8) 1 0 jp4 set to the same polarity as sw1-7 (vd9) 1 0 jp5 xscl2 clock for passive color 8-bit single 640x480 lcd panel (format 1) (see functional specification, x07-sp-001-xx) nc xscl2
page 10 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 lcd signal connector pinout table 2-4: lcd signal connector j1 pinout s1d13503 pin name lcd connector pin no. color stn lcd mono stn lcd 16-bit single/dual 8-bit dual 8-bit single (format 1 a ) aux[03] bit 3 =0, aux[01] bit 2=1 a see sections 7.4.3 and 7.4.5 of the s1d13503 hardware functional specification, x18a-a-001.01, for details. 8-bit single (format 2 a ) aux[03] bit 3 =1, aux[01] bit 2=1 4-bit 8-bit 4-bit ld0 1 ld0 ld0 ld0 ld0 ld0 ld1 3 ld1 ld1 ld1 ld1 ld1 ld2 5 ld2 ld2 ld2 ld2 ld2 ld3 7 ld3 ld3 ld3 ld3 ld3 ud0 9 ud0 ud0 ud0 ud0 ud0 ud0 ud0 ud1 11 ud1 ud1 ud1 ud1 ud1 ud1 ud1 ud2 13 ud2 ud2 ud2 ud2 ud2 ud2 ud2 ud3 15 ud3 ud3 ud3 ud3 ud3 ud3 ud3 17 ld4 b b from external logic; see section 3.5 for details. 19 ld5 b 21 ld6 b 23 ld7 b 25 ud4 b 27 ud5 b 29 ud6 b 31 ud7 b xscl 33 xscl xscl xscl xscl xscl xscl xscl wf/xscl2 35 xscl2 lp 37 lp lp lp lp lp lp lp yd 39 yd yd yd yd yd yd yd grnd 2-26 (even pins) grnd grnd grnd grnd grnd grnd grnd n/c 28 vlcd 30 vlcd vlcd vlcd vlcd vlcd vlcd vlcd vcc 32 +5 v +5 v +5 v +5 v +5 v +5 v +5 v +12 v 34 +12 v +12 v +12 v +12 v +12 v +12 v +12 v vddh 36 vddh vddh vddh vddh vddh vddh vddh wf/xscl2 38 wf wf wf wf wf wf lcdenb 40 /lcdpwr /lcdpwr /lcdpwr /lcdpwr /lcdpwr /lcdpwr /lcdpwr
epson research and development page 11 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 cpu / bus interface connector pinouts table 2-5: cpu/bus connector h1 pinout connector pin no. cpu/bus pin name comments 1 sd0 connected to db0 of the s1d13503 2 sd1 connected to db1 of the s1d13503 3 sd2 connected to db2 of the s1d13503 4 sd3 connected to db3 of the s1d13503 5 gnd ground 6 gnd ground 7 sd4 connected to db4 of the s1d13503 8 sd5 connected to db5 of the s1d13503 9 sd6 connected to db6 of the s1d13503 10 sd7 connected to db7 of the s1d13503 11 gnd ground 12 gnd ground 13 sd8 connected to db8 of the s1d13503 14 sd9 connected to db9 of the s1d13503 15 sd10 connected to db10 of the s1d13503 16 sd11 connected to db11 of the s1d13503 17 gnd ground 18 gnd ground 19 sd12 connected to db12 of the s1d13503 20 sd13 connected to db13 of the s1d13503 21 sd14 connected to db14 of the s1d13503 22 sd15 connected to db15 of the s1d13503 23 reset connected to the reset signal of the s1d13503 24 gnd ground 25 gnd ground 26 gnd ground 27 +12v 12 volt supply 28 +12v 12 volt supply 29 /sbhe connected to the bhe# signal of the s1d13503 30 iochrdy connected to the ready signal of the s1d13503 31 /iosc connected to the iocs# signal of the s1d13503 32 /memcs connected to the memcs# signal of the s1d13503
page 12 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 table 2-6: cpu/bus connector h2 pinout connector pin no. cpu/bus pin name comments 1 sa0 connected to ab0 of the s1d13503 2 sa1 connected to ab1 of the s1d13503 3 sa2 connected to ab2 of the s1d13503 4 sa3 connected to ab3 of the s1d13503 5 sa4 connected to ab4 of the s1d13503 6 sa5 connected to ab5 of the s1d13503 7 sa6 connected to ab6 of the s1d13503 8 sa7 connected to ab7 of the s1d13503 9 gnd ground 10 gnd ground 11 sa8 connected to ab8 of the s1d13503 12 sa9 connected to ab9 of the s1d13503 13 sa10 connected to ab10 of the s1d13503 14 sa11 connected to ab11 of the s1d13503 15 sa12 connected to ab12 of the s1d13503 16 sa13 connected to ab13 of the s1d13503 17 gnd ground 18 gnd ground 19 sa14 connected to ab14 of the s1d13503 20 sa15 connected to ab14 of the s1d13503 21 sa16 connected to u2 pin 20 22 sa17 connected to ab17 of the s1d13503 23 sa18 connected to ab18 of the s1d13503 24 sa19 connected to ab19 of the s1d13503 25 gnd ground 26 gnd ground 27 +5v 5 volt supply 28 +5v 5 volt supply 29 /iow connected to the iow# signal of the s1d13503 30 /ior connected to the ior# signal of the s1d13503 31 /smemw connected to the memw# signal of the s1d13503 32 /smemr connected to the memr# signal of the s1d13503
epson research and development page 13 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 3 technical description 3.1 isa bus support this board directly supports the 8/16-bit isa bus with indexed i/o via a standard at edge connector. only those config- uration resistors needed for isa bus support have been assembled, refer to hard-wired configuration inputs, on page 9 for configuration details. external logic has been added to provide signals which the s1d13503 does not directly support. see application note x18a-g-003-xx for details. this board is pre-set to use indexed i/o with base address 000 0011 0yyy 000x, where x is don ? t care and yyy can be configured through dip-switch sw1-7 to sw1-5. the factory setting of yyy = 001, i.e., i/o address = $0310 and $0311. the display memory bank address is described in sram support, on page 14. example: i/o write $310 01 :set index = 1 i/o read $311 :read contents of aux[1] i/o write $310 05 :set index = 5 i/o write $311 07 :write 07 to aux[5] this board has been designed to operate as a stand-alone card or in conjunction with either a vga or a monochrome display adapter card. with vga when the vga display adapter used is an isa or vl bus with an 8-bit bios eprom (normally just one rom on the adapter card) the s5u13503b00c must be configured as follows: sw1-1 open : 8-bit operation, necessary to prevent memcs16# conflict when reading vga bios sw1-2 to 4 open : for isa bus support with indexed i/o sw1-5 to 7 : set as desired jp1 2-3 shorted : to reflect sw1-1 polarity jp2 to jp4 : to reflect sw1-5 to 7 polarity jp5 : set as required for panel when the isa or vl bus vga video adapter has a 16-bit bios eprom (normally two roms on the adapter card), the 16-bit isa bus interface (sw-1 closed) must be used on the s5u13503b00c. when using the s5u13503b00c in conjunction with a pci bus vga display adapter either the 16-bit isa bus interface or the 8-bit isa bus interface may be used on the s5u13503b00c. with monochrome when using the s5u13503b00c in conjunction with a monochrome display adapter either the 16-bit isa bus interface or the 8-bit isa bus interface may be used on the s5u13503b00c. stand-alone the s5u13503b00c can be used as a stand-alone video adapter. when used as a stand-alone video adapter the bios setup program for the computer must support and have ? no video ? selected as the video adapter. the 13503bios.com utility program can be used with the evaluation board to simulate a standard video bios, thus providing text and cursor function- ality. see the 13503bios.com utility manual, x18a-b-003-xx for details.
page 14 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 3.2 non-isa bus support this evaluation board was specifically designed to support the standard 8/16-bit isa bus. however, as the s1d13503 does support other bus interfaces, header strips have been provided containing all necessary i/o pins. (see table 2-1, configu- ration dip switch settings, on page 8, hard-wired configuration inputs, on page 9, and cpu/bus interface header strips, on page 16, for details.) when using the header strips to provide the bus interface observe the following: 1. all i/o signals on the isa bus card edge must be isolated from the isa bus (do not plug the card into a computer). voltage lines are provided on the header strips. 2. u2, a tibpal22v10 pal, is currently used to provide the s1d13503 iocs# (pin 23) and memcs# (pin 22) input signals for isa bus use. this functionality must now be provided externally as u2 must be removed. 3. linear addressing of the entire 128k bytes of video ram is available. due to the memory banking method used for isa bus support, u2 must be removed and h2, pin 21, must be physically connected to u2, pin20, in order to provide sa16 to u1. 4. if it becomes necessary / desirable to change the configuration information associated with vd[15:0], additional 10k ohm pull-up resistors can be added to those affected vd lines as there are place holders available on the pcb. 3.3 sram support the s5u13503b00c board supports 16-bit wide, 128k byte sram. in order for the s5u13503b00c to operate in conjunction with a vga card and not cause memory space conflicts, all 128k bytes of memory is available through two 64k byte banks. the first 64k bank is selected by reading from the base i/o mapping address + 2 (address $312 if the i/o address is $310) and the second 64k bank is selected by writing to i/o address + 2 (address $312 if the i/o address is $310). the display memory banks reside at the 64k byte memory segment $d. i/o read $312 :select memory bank 0 i/o write $312 :select memory bank 1 3.4 monochrome lcd support the s1d13503 directly supports 4/8-bit dual and single monochrome lcd panels. all the necessary signals are provided on the 40-pin ribbon cable header. the interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems. refer to table 2-4, lcd signal connector j1 pinout, on page 10 for specific settings.
epson research and development page 15 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 3.5 color lcd support the s5u13503b00c directly supports 4/8/16-bit dual and single color lcd panels. all the necessary signals are provided on the 40-pin ribbon cable header. the interface signals are alternated with grounds on the cable to reduce cross talk and noise related problems. to facilitate interfacing a 16-bit panel to the s1d13503, the following external circuit is implemented on-board: this circuit provides 16-bit color panel support by latching the 8 bits of output data from the s1d13503 to provide 16 bits of data on the next clock. refer to table 2-4, lcd signal connector j1 pinout, on page 10 for specific settings. 3.6 power save modes the s1d13503 supports two software power save modes. the utility program 13503pd.exe is supplied to control these software modes. the software modes are controlled by directly writing the s1d13503 associated internal registers. 3.7 adjustable lcd panel negative power supply the majority of monochrome lcd panels require a negative power supply to provide between -18 v and -23 v (i out =45ma). for ease of implementation, such a power supply has been provided as an integral part of this design. the signal vlcd can be adjusted by r11 (100k potentiometer) to provide an output voltage from -14 v to -23 v and enabled/disabled by the control signal lcdenb. note lcdenb is directly controlled by register aux[01], bit 4, of the s1d13503. the vlcd power supply used on the s5u13503b00c requires a logic ? 1 ? to disable it. as the signal lcdenb is a logic ? 0 ? at power-up, it is inverted by external logic to disable vlcd and prevent damaging the panel connected to the s5u13503b00c. determine the panel ? s specific power requirements and set the potentiometer accordingly before connecting the panel. 3.8 adjustable lcd panel positive power supply the majority of lcd passive color panels and most single monochrome 640x480 stn lcd panels require a positive power supply to provide between +23v and +40v (i out =45ma). for ease of implementation, such a power supply has been provided as an integral part of this design. the signal vddh can be adjusted by r8 (100k potentiometer) to provide an output voltage from +23 v to +40 v and enabled/disabled by the control signal lcdenb. note lcdenb is directly controlled by register aux[01], bit 4, of the s1d13503. the vddh power supply used on the s5u13503b00c requires a logic ? 1 ? to disable it. as the signal lcdenb is a logic ? 0 ? at power-up, it is invert- ed by external logic to disable vlcd and prevent damaging the panel connected to the s5u13503b00c. determine the panel ? s specific power requirements and set the potentiometer accordingly before connecting the panel. ud[3:0] ld[3:0] xscl ud[3:0] ld[3:0] ud[7:4] ld[7:4] to 16-bit panel from s1d13503 d q ck 74ls374
page 16 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 3.9 crystal support the input crystal frequency may be up to 25.0 mhz depending on the specific panel size and frame rate desired. refer to section 9.3 of the s1d13503 functional specification , drawing office no. x18a-a-001-xx for further details. 3.10 oscillator support the input oscillator frequency used may be up to 25.0 mhz, depending on the specific panel size and frame rate desired. refer to section 9.3 of the s1d13503 functional specification , drawing office no. x18a-a-001-xx for further details. note when the oscillator package is used capacitors c7, c8 and resistor r16 must be removed. 3.11 cpu/bus interface header strips all of the cpu/bus interface pins of s1d13503, with the exception of sa16, are connected to the header strips h1 and h2 for easy interface to a cpu/bus other than the isa bus. refer to table 2-5, cpu/bus connector h1 pinout, on page 11 and table 2-6, cpu/bus connector h2 pinout, on page 12 for specific settings. note these headers only provide the cpu/bus interface signals from s1d13503, when mc68000 interface is selected (sw1- 3 closed), external decoding logic must be used to access the s1d13503. 3.12 schematic notes this evaluation board may have been modified and therefore the following schematics may not reflect the actual imple- mentation. please request updated information before starting any hardware design.
epson research and development page 17 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 appendix a parts list item # qty/board designation part value description 1 13 c11-c23 0.01uf 0.01uf, 1206 pckg 2 2 c9 -c10 10uf 10uf / 25v tantalum d-size 3 2 c7-c8 7pf 7pf, 1206 pckg 4 3 c2-c4 10uf / 63v electrolytic / radial (lxf63vb10rm5x11ll) 5 3 c1, c5, c6 56uf/35v lxf35vb56rm6x11ll 6 2 h1, h2 con32a 32-pin dual row header 7 5 jp1-jp5 header 3 3-pin single row header 8 1 j1 con40a shrouded header 40 pin dual-row center-key pth 9 1 l1 1uh dale inductor im-4-1.0uh pth 10 2 l2-l3 ferrite bead fair-rite 2743001111 11 1 q1 2n3906 pnp signal transistor to-92 pth 12 1 q2 2n3903 npn signal transistor to-92 pth 13 3 r2, r13, r14 1k 1k ohm/1206/5% 14 2 r12, r15 100k 100k ohm/1206/5% 15 4 r3-r6 10k 10k ohm/1206/5% 16 1 r7 470k 470k ohm/1206/5% 17 1 r8 200k 200k ohm trim pot spectrol 63s204t607 18 1 r9 10k 10k 10-pin sip, part no. 4610x-101-103 19 1 r10 14k 14k ohm/1206/5% 20 1 r11 100k 100k ohm trim pot spectrol 63s104t607 21 1 r16 2m 2m ohm/1206/5% 22 1 r1 0 ohm 0 ohm / 1206 / 1% 23 5 r17-r21 10k 10k ohm/1206/5% 24 1 s1 sw-dip-8 dip switch 8-position 25 1 u1 s1d13503 qfp5-100-s2 26 1 u2 tibpal22v10 texas ins. pal, socketed 27 2 u3, u4 74ls688 dw020 smt package 28 1 u5 74ls09 d014 smt package 29 2 u6, u7 srm20100ltm-70 128k x 8 sram 30 1 u8 rd-0412 xentek - positive power supply 31 1 u9 epn001 xentek - negative power supply 32 1 u10 osc-14 14-pin socket for 25.0mhz, 12.0mhz, and 6.0mhz 14- pin oscillators 33 1 u11 74ls374 dw020 smt package 34 1 y1 25.175mhz crystal
page 18 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 appendix b s5u13503b00c rev. 1.0 schematic diagrams figure 1: s5u13503b00c rev. 1.0 schematic diagram (1 of 7) date: december 13, 1996 sheet 1 of 7 size document number rev b 13503-1.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems inc. sd[0..15] ld[0..3] sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 ld0 ld1 ld2 ld[0..3] sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 sa17 sa18 sa19 ab0 12 ab1 13 ab2 14 ab3 15 ab4 16 ab5 17 ab6 18 ab7 19 ab8 20 ab9 21 ab10 22 ab11 23 ab12 24 ab13 25 ab14 26 ab15 27 ab17 29 ab19 31 iocs# 84 iow# 85 ior# 86 memcs# 87 memw# 88 memr# 89 osc1 92 osc2 93 reset 32 db0 94 db1 95 db2 96 db3 97 db4 98 db5 99 db6 100 db7 1 db8 4 db9 5 db10 6 db11 7 db12 8 db13 9 db14 10 db15 11 ld0 77 ld1 76 ld2 75 ld3 74 ud0 73 ud1 72 ud2 71 ud3 70 wf/xscl2 80 lp 79 yd 78 xscl 81 va1 34 va2 35 va3 36 va4 37 va5 38 va6 39 va7 40 va8 41 va9 42 va12 63 va13 64 va14 65 va15 66 vd0 44 vd1 45 vd2 46 vd3 47 vd4 48 vd5 49 vd6 50 vd7 51 vd8 54 vd9 55 vd10 56 vd11 57 vd12 58 vd13 59 vd14 60 vd15 61 vwe# 67 voe# 83 vcs0# 68 vcs1# 69 va11 62 lcdenb 82 va0 33 va10 43 ab16 28 ab18 30 bhe# 91 ready 90 vss 52 vss 2 vdd 53 vdd 3 u1 s1d13503 new-sa16 sa[0..19] osc1 osc2 /sbhe /iocs /iow /ior /memcs reset /smemw /smemr new-sa16 osc1 osc2 /sbhe /iocs /iow /ior /memcs reset /smemw /smemr ld3 ud0 ud1 ud2 ud3 lp yd xscl lcdenb va0 va1 va2 va3 va4 va5 va6 va7 va8 va9 va10 va11 va12 va13 wf/xscl2 ud[0..3] lp yd xscl lcdenb wf/xscl2 ud[0..3] iochrdy va[0..15] vd[0..15] /vwe /voe /vcs0 /vcs1 va14 va15 vd0 vd1 vd2 vd3 vd4 vd5 vd6 vd7 vd8 vd9 vd10 vd11 vd12 vd13 vd14 vd15 /vwe /voe /vcs0 /vcs1 iochrdy +5v +12v +12v +5v vss +5v gnd r1 0
epson research and development page 19 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 figure 2: s5u13503b00c rev. 1.0 schematic diagram (2 of 7) date: december 13, 1996 sheet 2 of 7 size document number rev b 13503-2.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems, inc. /iocs /memcs new-sa16 +5v lcdenb refresh /ioen /iocs16en lcdenb /ioen refresh /lcdenb clk/in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8 in 9 in 10 in 11 gnd 12 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 in 13 vcc 24 u2 tibpal22v10 /ior /iow new-sa16 sa11 sa12 sa13 sa14 sa15 sa16 sa17 sa18 sa19 sa1 /iodc2to10 sa[1..19] 1 2 3 jp4 header 3 1 2 3 jp3 header 3 +5v +5v sa5 sa6 sa7 sa8 sa9 addbit4 addbit5 addbit6 +5v p0 2 p1 4 p2 6 p3 8 p4 11 p5 13 p6 15 p7 17 q0 3 q1 5 q2 7 q3 9 q4 12 q5 14 q6 16 q7 18 g 1 /p=q 19 vcc 20 gnd 10 u3 74ls688 dw020 1 2 3 u5a 74ls09 d014 +5v r2 1k /memcs16 /lcdpwr /iocs16 4 5 6 u5b 74ls09 d014 9 10 8 u5c 74ls09 d014 12 13 11 u5d 74ls09 d014 sa2 sa3 sa4 +5v la17 la18 la19 la20 la21 la22 la23 sa10 p0 2 p1 4 p2 6 p3 8 p4 11 p5 13 p6 15 p7 17 q0 3 q1 5 q2 7 q3 9 q4 12 q5 14 q6 16 q7 18 g 1 /p=q 19 vcc 20 gnd 10 u4 74ls688 dw020 1 2 3 jp1 header 3 1 2 3 jp2 header 3 /8bitbi 16-bit interface = 1 8-bit interface = 0 +12v +12v +5v vss +5v gnd la[17..23] memory address = c segment or c & d segments +5v unused gate
page 20 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 figure 3: s5u13503b00c rev. 1.0 schematic diagram (3 of 7) date: december 12, 1996 sheet 3 of 7 size document number rev b 13503-3.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems inc. vd8 vd9 (iobit6) (iobit5) 12345678 1 6 1 5 1 4 1 3 1 2 1 1 1 09 s1 sw dip-8 1 1 0 r9i 10k 1 9 r9h 10k 1 8 1 2 r9a 10k 1 3 1 4 1 5 1 6 1 7 r3 10k r4 10k r5 10k r6 10k r17 10k +5v r18 10k r19 10k r20 10k r21 10k for 68000 mpu support vd[0..15] vd[0..15] vd15 vd14 vd12 vd11 vd0 vd1 vd2 vd3 vd7 (iobit4) (no byteswap) (isa) (indexing) (8bitbi) vd13 vd10 vd6 vd5 vd4 a0 20 a1 19 a2 18 a3 17 a4 16 a5 15 a6 14 a7 13 a8 3 a9 2 a10 31 a11 1 a12 12 a13 4 a14 11 oe 32 do1 21 do2 22 do3 23 do4 25 do5 26 do6 27 do7 28 do8 29 a15 7 we 5 cs1 30 cs2 6 vdd 8 vss 24 a16 10 nc 9 u7 srm20100ltm-70 +5v +5v vd8 vd9 vd10 vd11 vd12 vd13 vd14 vd15 va0 va1 va2 va3 va4 va5 va6 va7 va8 va9 va10 va11 va12 va13 va14 va15 va0 va1 va2 va3 va4 va5 va6 va7 va8 va9 va10 va11 va12 va13 va14 va15 vd0 vd1 vd2 vd3 vd4 vd5 vd6 vd7 +5v a0 20 a1 19 a2 18 a3 17 a4 16 a5 15 a6 14 a7 13 a8 3 a9 2 a10 31 a11 1 a12 12 a13 4 a14 11 oe 32 do1 21 do2 22 do3 23 do4 25 do5 26 do6 27 do7 28 do8 29 a15 7 we 5 cs1 30 cs2 6 vdd 8 vss 24 a16 10 nc 9 u6 srm20100ltm-70 va[0..15] +5v +12v +12v +5v vss +5v gnd /voe /vwe /vcs0 /voe /vwe /vcs0 /vcs1 /vcs1
epson research and development page 21 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 figure 4: s5u13503b00c rev. 1.0 schematic diagram (4 of 7) date: december 13, 1996 sheet 4 of 7 size document number rev b 13503-4.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems inc. +5v vlcd 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 j1 con40a ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 mono/color lcd connector ld4 ld5 ld6 ld7 ud4 ud5 ud6 ud7 ld[0..3] ud[0..3] ld[0..3] ud[0..3] xscl lp yd wf/xscl2 ld0 ld1 ld2 ld3 ud0 ud1 ud2 ud3 xscl lp yd d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oc 1 clk 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 vcc 20 gnd 10 u11 74ls374 dw020 xscl2 1 2 3 jp5 header 3 +12v /lcdpwr vddh /lcdpwr ld4 ld5 ld6 ld7 ud4 ud5 ud6 ud7 +5v wf/xscl2 wf/xscl2 sa1 sa3 sa5 sa7 sa9 sa11 sa13 sa15 sa17 sa19 /ior /smemr +5v gnd gnd gnd sa0 sa2 sa4 sa6 sa8 sa10 sa12 sa14 sa16 sa18 /iow /smemw +5v gnd gnd gnd 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 h2 con32a sd1 sd3 sd5 sd7 sd9 sd11 sd13 sd15 iochrdy /memcs +12v gnd gnd gnd gnd gnd 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 h1 con32a sd0 sd2 sd4 sd6 sd8 sd10 sd12 sd14 /sbhe reset /iocs +12v gnd gnd gnd gnd +12v +12v +5v vss +5v gnd cpu/bus i/f
page 22 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 figure 5: s5u13503b00c rev. 1.0 schematic diagram (5 of 7) date: december 12, 1996 sheet 5 of 7 size document number rev b 13503-5.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems inc. reset +5v gnd 1 reset 2 +5v 3 irq9 4 -5v 5 drq2 6 -12v 7 ows 8 +12v 9 gnd 10 /smemw 11 /smemr 12 /iow 13 /ior 14 /dack3 15 drq3 16 /dack1 17 drq1 18 /refresh 19 clk 20 irq7 21 irq6 22 irq5 23 irq4 24 irq3 25 /dack2 26 t/c 27 bale 28 +5v 29 osc 30 gnd 31 at2 at con-b /iochck 1 sd7 2 sd6 3 sd5 4 sd4 5 sd3 6 sd2 7 sd1 8 sd0 9 iochrdy 10 aen 11 sa19 12 sa18 13 sa17 14 sa16 15 sa15 16 sa14 17 sa13 18 sa12 19 sa11 20 sa10 21 sa9 22 sa8 23 sa7 24 sa6 25 sa5 26 sa4 27 sa3 28 sa2 29 sa1 30 sa0 31 at1 at con-a sd7 sd6 sd5 sd4 sd3 iochrdy /ioen sd2 sd1 sd0 sa19 sa18 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 +12v /smemw /smemr /iow /ior refresh /memcs16 /iocs16 +5v /memcs16 1 /iocs16 2 irq10 3 irq11 4 irq12 5 irq15 6 irq14 7 /dack0 8 drq0 9 /dack5 10 drq5 11 /dack6 12 drq6 13 /dack7 14 drq7 15 +5v 16 master 17 gnd 18 at4 at con-d /sbhe 1 la23 2 la22 3 la21 4 la20 5 la19 6 la18 7 la17 8 /memr 9 /memw 10 sd8 11 sd9 12 sd10 13 sd11 14 sd12 15 sd13 16 sd14 17 sd15 18 at3 at con-c sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 la23 la22 la21 la20 la19 la18 la17 /sbhe sa[0..19] sd[0..15] la[17..23] +12v +12v +5v vss +5v gnd
epson research and development page 23 vancouver design center s5u13503b00c rev. 1.0 evaluation board user manual s1d13503 issue date: 01/01/30 x18a-g-007-05 figure 6: s5u13503b00c rev. 1.0 schematic diagram (6 of 7) date: december 12, 1996 sheet 6 of 7 size document number rev b 13503-6.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems inc. vddh adjustable 23v to 40v 1 2 l1 1uh v o u t _ a d j 1 d c _ i n 2 r e m o t e 3 g n d 4 g n d 5 g n d 6 g n d 7 g n d 8 n c 9 g n d 1 0 g n d 1 1 d c _ o u t 1 2 u8 rd-0412 r7 470k c1 56uf/35v psvcc 1 3 2 r8 200k r10 14k +5v c2 10uf/63v c3 10uf/63v c4 10uf/63v low esr low esr r13 1k psgnd 2 1 3 q1 2n3906 2 1 3 q2 2n3903 vlcd adjustable -14v to -23v r12 100k r14 1k r15 100k c5 56uf/35v d c _ o u t 1 d c _ o u t 2 n c 3 g n d 4 g n d 5 v o u t _ a d j 6 n c 7 n c 8 n c 9 d c _ i n 1 1 d c _ i n 1 0 u9 epn001 1 3 2 r11 100k psvcc /lcdpwr +12v +12v +5v vss +5v gnd 1 2 l2 1 2 l3 +5v psvcc psgnd c6 56uf/35v psgnd
page 24 epson research and development vancouver design center s1d13503 s5u13503b00c rev. 1.0 evaluation board user manual x18a-g-007-05 issue date: 01/01/30 figure 7: s5u13503b00c rev. 1.0 schematic diagram (7 of 7) date: december 13, 1996 sheet 7 of 7 size document number rev b 13503-7.sch 1.0 title s5u13503b00c smd isa-bus evaluation board s-mos systems, inc. +5v when the oscillator package is used, the stabilizing capacitors and resistor must be removed. nc 1 out 8 gnd 7 vcc 14 u10 osc-14 osc1 osc2 1 4 y1 25.175mhz r16 2m +5v c11 .01uf c12 .01uf bypass capacitors (1/power pin) c7 7pf c8 7pf c13 .01uf c14 .01uf c15 .01uf c16 .01uf c17 .01uf c18 .01uf c19 .01uf c22 .01uf c20 .01uf c21 .01uf c23 .01uf +12v +5v +12v +12v +5v vss +5v gnd c9 10uf c10 10uf
s1d13503 dot matrix graphics lcd controller power consumption document number: x18a-g-006-04 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center power consumption s1d13503 issue date: 01/01/30 x18a-g-006-04 1 s1d13503 power consumption 1.1 conditions table 1-1: s1d13503 total power consumption - 3.0v operation test condition gray shades / colors total power consumption active power save mode 12 1 input clock = 6 mhz lcd panel connected = 320x240 monochrome v dd = 3.0v black-and-white 4 grays 16 grays 5.4 mw 6.4 mw 7.6 mw 1.2 mw 1.2 mw 1.2 mw less than 300 uw less than 300 uw less than 300 uw 2 input clock = 6 mhz lcd panel connected = 320x240 color v dd = 3. v 4 colors 16 colors 256 colors 8.8 mw 10.3 mw 12.7 mw 1.2 mw 1.2 mw 1.2 mw less than 300 uw less than 300 uw less than 300 uw 3 input clock = 25 mhz lcd panel connected = 640x480 monochrome v dd = 3.0v black-and-white 4 grays 19.7 mw 24.3 mw 2.7 mw 2.7 mw less than 300 uw less than 300 uw 4 input clock = 25 mhz lcd panel connected = 640x480 color v dd = 3.0v 4 colors 33.1 mw 2.7 mw less than 300 uw table 1-2: s1d13503 total power consumption - 5.0v operation test condition gray shades / colors total power consumption active power save mode 12 1 input clock = 6 mhz lcd panel connected = 320x240 monochrome v dd = 5.0v black-and-white 4 grays 16 grays 26.0 mw 29.7 mw 35.7 mw 10.5 mw 10.5 mw 10.5 mw 1.2 mw 1.2 mw 1.2 mw 2 input clock = 6 mhz lcd panel connected = 320x240 color v dd = 5.0v 4 colors 16 colors 256 colors 37.8 mw 44.5 mw 52.8 mw 10.5 mw 10.5 mw 10.5 mw 1.2 mw 1.2 mw 1.2 mw 3 input clock = 25 mhz lcd panel connected = 640x480 monochrome v dd = 5.0v black-and-white 4 grays 76.0 mw 92.0 mw 16.7 mw 16.7 mw 1.0 mw 1.0 mw 4 input clock = 25 mhz lcd panel connected = 640x480 color v dd = 5.0v 4 colors 120.8 mw 16.7 mw 1.0 mw
page 4 epson research and development vancouver design center s1d13503 power consumption x18a-g-006-04 issue date: 01/01/30 s1d13503 total power consumption - 3v 0 5 10 15 20 25 30 35 active psm 1 psm 2 operating mode p o w e r m w condition 1 - bw condition 1 - 4 grays condition 1 - 16 grays condition 2 - 4 color condition 2 - 16 color condition 2 - 256 color condition 3 - bw condition 3 - 4 color condition 4 - 4 color s1d13503 total power consumption - 5v 0 20 40 60 80 100 120 140 active psm 1 psm 2 operating mode p o w e r m w condition 1 - bw condition 1 - 4 grays condition 1 - 16 grays condition 2 - 4 color condition 2 - 16 color condition 2 - 256 color condition 3 - bw condition 3 - 4 color condition 4 - 4 color
s1d13503 dot matrix graphics lcd controller isa bus interface considerations document number: x18a-g-003-05 copyright ? 1995, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center isa bus interface considerations s1d13503 issue date: 01/01/30 x18a-g-003-05 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 reference material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 16-bit isa bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pal equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 additional discrete logic description . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 s1d13503 default setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.1 configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.2 register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 8-bit isa bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 s1d13503 default setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.2 register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 list of figures figure 1: 16-bit isa bus implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2: 8-bit isa bus implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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epson research and development page 5 vancouver design center isa bus interface considerations s1d13503 issue date: 01/01/30 x18a-g-003-05 1 introduction the s1d13503 is a general purpose lcd controller capable of interfacing to a variety of microprocessors. in some cases this interface is accomplished through the use of minimal external circuitry. this application note describes the interface between the s1d13503 and the isa bus both 8 and 16-bit implementations. 1.1 reference material refer to the s1d13503 hardware functional specification (x18a-a-001-xx) for complete ac timing details. this document makes no attempts to describe the operation of the isa bus, please refer to the appropriate isa bus documentation for complete information.
page 6 epson research and development vancouver design center s1d13503 isa bus interface considerations x18a-g-003-05 issue date: 01/01/30 2 16-bit isa bus interface for the purpose of the example shown below, the following conditions apply: 1. indexed i/o with addresses 0310h and 0311h (see configuration options) 2. 128kbytes of display memory occupying $c and $d segments (see configuration options) note this memory configuration will conflict with a vga card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. this section provides the necessary logic equations and settings to complete the interface between the s1d13503 and the 16-bit isa bus. note a pal was used instead of discrete logic to reduce external component count. figure 1: 16-bit isa bus implementation a 1 2 3 iocs# memcs# ab0-19 bhe# db0-15 memw memr iow# ior# ready b 74ls09 4 5 6 aen refresh sa0-19 sbhe# sd0-15 smemw# smemr# iow# ior# iochrdy 10k ? v cc vd0,vd7, vd14-15 vd11-12, iocs16# la17-23 memcs16# 74ls688 0000110 (q0-6) la23-17 (p0-6) p q g iocs16en pa l 16-bit isa bus s1d13503 sa1-15
epson research and development page 7 vancouver design center isa bus interface considerations s1d13503 issue date: 01/01/30 x18a-g-003-05 2.1 pal equations the pal is programmed with the following equations: note a ? ! ? placed before a signal name indicates a logic ? 0 ? state. a ? & ? indicates a logic ? and ? function. 1. as stated above, the default i/o address is from 0310h to 0311h. the s1d13503 provides internal decoding of ad- dress bits a0 to a9, therefore minimal external circuitry is necessary to provide signals iocs# and iocs16# iocs# is required by the s1d13503 to indicate a valid i/o cycle. in an isa bus environment, valid i/o decoding must include addresses a15-a0. as a0-a9 are decoded internally, the equation must only guarantee that addresses a10-15 must all be ? 0 ? and aen must also be ? 0 ? . iocs# = !(!aen & !a15 & !a14 & !a13 & !a12 & !a11 & !a10) 2. as the s1d13503 is capable of 16-bit i/o access, the iocs16# bus signal must be driven externally to indicate such a cycle. as stated in the isa specification, the iocs16# is a straight address decode without qualification. iocs16en# = !(!iocs# & a9 & a8 & !a7 & !a6 & !a5 & a4 & !a3 & !a2 & !a1) 3. with 128kbytes of display memory and a17 to a19 decoded internally to s1d13503; memcs# = !refresh note the msbs of the address (a23:a20) need not be externally decoded if using smemw# and smemr# as they will only assert on addresses < 1mb. 2.2 additional discrete logic description 1. as shown in figure 1, the 74ls688 is configured as a memory decoder with valid addresses between 0c0000h and 0dffffh. this provides the memcs16# signal allowing for 16-bit memory cycles. as stated in the isa specifica- tion, the memcs16# is a straight address decode without qualification. 2. the 74ls09 is used simply to provide the open-collector outputs necessary for the iocs16# and memcs16# sig- nals. 2.3 s1d13503 default setup 2.3.1 configuration options the s1d13503 latches the state of the sram data bus during reset to determine the power-on configuration. the chip has internal pull-down resistors and therefore external pull-ups are only necessary when requiring a ? 1 ? state, see below. 1. vd15 - vd13 = 110 memory decoding for locations $c and $d segments 2. vd12 - vd4 = 110001000 i/o decoding for locations 0310h and 0311h (1100010000b - 1100010001b) 3. vd3 = 0 no byte swap of high and low bytes 4. vd2 = 0 isa bus interface, i.e. non- mc68k interface 5. vd1 = 0 indexed i/o 6. vd0 = 1 16-bit bus interface where 1 = pull-up with a 10k resistor; 0 = no pull-up resistor
page 8 epson research and development vancouver design center s1d13503 isa bus interface considerations x18a-g-003-05 issue date: 01/01/30 2.3.2 register setting all register settings are completely programmable with the following exceptions: - memory interface, aux[1] bit 1 = 0 for 16-bit memory interface. note this bit is forced = 0 when 16-bit cpu interface is selected through vd0 on power-up. - rams, aux[1] bit 0, this bit is ignored in 16-bit memory configurations. all other registers are dependent on display type, resolution, color and mode of operation, see functional specification for details.
epson research and development page 9 vancouver design center isa bus interface considerations s1d13503 issue date: 01/01/30 x18a-g-003-05 3 8-bit isa bus interface for the purpose of the example shown below, the following conditions apply: 1. indexed i/o with partial decoding, i.e. address lines a10 to a15 are not decoded for i/o cycles note partial decoding is quite safe on most isa bus systems as i/o addresses above 03ffh are rarely used. 2. i/o addresses are 0300h and 0301h (xxxxxx1100000000b and xxxxxx1100000001b) 3. 64kbytes of display memory occupying $a segment note the 74ls00 is simply used to detect the $b segment and invalidate the memcs# input. note this memory configuration may conflict with a vga card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. this section provides the necessary settings to complete the interface between the s1d13503 and the 8-bit isa bus. since i/o addresses are partially decoded, there is no need to use a pal for decoding. figure 2: 8-bit isa bus implementation iocs# memcs# ab0-19 bhe# db0-7 memw memr iow# ior# ready a b sa16 74ls00 1 2 3 4 5 6 aen refresh sa0-19 sd0-7 smemw# smemr# iow# ior# iochrdy 10k ? v cc vd15 vd11-13, s1d13503 8-bit isa bus
page 10 epson research and development vancouver design center s1d13503 isa bus interface considerations x18a-g-003-05 issue date: 01/01/30 3.1 s1d13503 default setup 3.1.1 configuration options the s1d13503 latches the state of the sram data bus during reset to determine the power-on configuration. the chip has internal pull-down resistors and therefore external pull-ups are only necessary when requiring a ? 1 ? state, see below. 1. vd15 - vd13 = 101 memory decoding for locations $a segment 2. vd12 - vd4 = 110000000 i/o decoding for locations 1100000000b - 1100000001b 3. vd3 = 0 no byte swap of high and low bytes 4. vd2 = 0 isa bus interface, i.e. non- mc68k interface 5. vd1 = 0 indexed i/o 6. vd0 = 0 8-bit bus interface where 1 = pull-up with a 10k resistor; 0 = no pull-up resistor 3.1.2 register setting all register settings are completely programmable and are dependent on display type, resolution, color and mode of operation, see functional specification for details.
s1d13503 dot matrix graphics lcd controller mc68340 interface considerations document number: x18a-g-004-04 copyright ? 1996, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center mc68340 interface considerations s1d13503 issue date: 01/01/30 x18a-g-004-04 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 reference material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 mc68340 mpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 mc68340 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pal equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 s1d13503 default setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of figures figure 1: mc68340 mpu interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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epson research and development page 5 vancouver design center mc68340 interface considerations s1d13503 issue date: 01/01/30 x18a-g-004-04 1 introduction the s1d13503 is a general purpose lcd controller capable of interfacing to a variety of microprocessors. this interface is accomplished through the use of minimal external circuitry. this application note describes the interface between the s1d13503 and the 16-bit mc68340 microcontroller. 1.1 reference material refer to the s1d13503 hardware functional specification (x18a-a-001-xx) for complete ac timing details. this document makes no attempts to describe the operation of the mc68340 microcontroller, please refer to the appropriate mc68340 documentation for this information.
page 6 epson research and development vancouver design center s1d13503 mc68340 interface considerations x18a-g-004-04 issue date: 01/01/30 2 mc68340 mpu interface the following sections provide the necessary settings and equations to complete the interface between the s1d13503 and the mc68340 microcontroller. figure 1: mc68340 mpu interface block diagram 2.1 mc68340 setup for the purpose of this example, the following conditions apply: the internal chip select signal cs3 of the mc68340, along with external dsack1 response, is employed to access the s1d13503. direct mapping of the i/o with starting address at 00000000h, and 128kbytes of display memory with starting address 00020000h are also used. 1. cs3 with 256kbyte block size - starting address at 00000000h and ending address at 0003ffffh 2. external dsack1 response - 16-bit port 3. don ? t care function codes and with cpu space access 4. both read and write accesses are allowed settings for the address mask register and base address register for the above conditions are: 058h - 05bh = 0003ffffh address mask register 05ch - 05fh = 000000f5h base address register v cc 4.7k ? 10k ? v cc v cc vd0-vd3 vd13 a0 a10-a17 memcs# iocs# bhe# ab0-ab19 db0-db15 memr# memw# ior# iow# ready cs3 siz0 a0-a19 d0-d15 as r/w dsack1 mc68340 pa l s1d13503 reset reset
epson research and development page 7 vancouver design center mc68340 interface considerations s1d13503 issue date: 01/01/30 x18a-g-004-04 2.2 pal equations the pal is programmed with the following equations: 1. with direct-mapping i/o occupying locations from 00000000h to 0000000fh and a4 to a9 decoded internally to s1d13503; iocs# = !(!cs3 & !a17 & !a16 & !a15 & !a14 & !a13 & !a12 & !a11 & !a10) 2. with memory locations from 00020000h to 003ffffh and a17 to a19 decoded internally to s1d13503; memcs# = c s3 3. bhe# becomes valid for two conditions: 1. 16-bit or 32-bit cycle, i.e., siz0=0 2. 8-bit cycle with odd byte access, i.e., siz0=1 and a0=1; bhe# = siz0 & !a0 2.3 s1d13503 default setup configuration options 1. vd15 - vd13 = 001 memory decoding for locations 20000h - 3ffffh 2. vd12 - vd4 = 000000xxx i/o decoding for locations 0000000000b - 0000001111b 3. vd3 = 1 byte swap of high and low bytes 4. vd2 = 1 mc68k interface 5. vd1 = 1 direct-mapping i/o 6. vd0 = 1 16-bit bus interface where x = don ? t care; 1 = pull-up with a 10k resistor; 0 = no pull-up resistor note the states of these data pins are internally latched during reset. register setting aux[1] bit 1 = 0 for 16-bit memory interface (must be 16-bit with a 16-bit bus).
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s1d13503 dot matrix graphics lcd controller lcd panel options / memory requirements document number: x18a-g-005-05 copyright ? 1995, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center lcd panel options / memory requirements s1d13503 issue date: 01/01/30 x18a-g-005-05 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 reference material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 configuration equations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 input clock requirement calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 sram size and access time requirements . . . . . . . . . . . . . . . . . . . . . 7 2.2.1 sram size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.2 sram access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 16-bit display memory interface . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.1 configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.2 register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 list of figures figure 1: 16-bit memory configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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epson research and development page 5 vancouver design center lcd panel options / memory requirements s1d13503 issue date: 01/01/30 x18a-g-005-05 1 introduction the s1d13503 is a highly configurable general purpose lcd controller. the lcd panel frame-rate, resolution, and number of colors / gray shades all determine the memory and input clock requirements. this application note describes the equations used to determine the various parameters. an example resolution and desired frame-rate will be selected and used to determine the remaining variables. 1.1 reference material refer to the s1d13503 hardware functional specification (x18a-a-001-xx) for complete ac timing details.
page 6 epson research and development vancouver design center s1d13503 lcd panel options / memory requirements x18a-g-005-05 issue date: 01/01/30 2 configuration equations this application note will follow one example through all the required calculations. for a complete description of all formula and associated parameters refer to the hardware functional specification. 2.1 example lcd panel resolution: 320x240 lcd panel configuration: 8-bit, single panel, single drive panel lcd colors: 256 desired frame-rate: 70hz s1d13503 operating voltage: 3.3v 2.1.1 input clock requirement calculation for a frame rate of 70hz, the input clock (or pixel clock) frequency can be calculated as following: f osc = input clock where dhndp is default horizontal non-display period in term of pixels: dhndp = 16 pixels in gray shade display modes, and dhndp = 32 pixels in bw display mode and in color display modes. where phndp is programmable horizontal non-display period in term of pixels: phndp = 0 pixels when aux[0c] = 0, and phndp = pixels when aux[0c] not equal to zero. note for this example we will use dhndp = 32, phndp = 0 therefore: f osc = 70 * (320 + 32) * (240 + 4) f osc = 6.0 mhz f osc framerate numberofhorizontalpixels phndp dhndp ++ () numberofverticallines 4 + () = aux 0 c [] 1 + () memoryinterfacewidth () bitsperpixel () ---------------------------------------------------------------------------------------------------------------- -
epson research and development page 7 vancouver design center lcd panel options / memory requirements s1d13503 issue date: 01/01/30 x18a-g-005-05 2.2 sram size and access time requirements 2.2.1 sram size memory size (bytes) = i.e., 256 colors = 8 bits / pixel, therefore 1 byte (8 bits) = 1 pixel therefore: memory size (bytes) = (320 * 240) * 8 /8 memory size (bytes) = 76.8 k bytes. note for a detailed description of the memory size requirement, see section 9.4 of the s1d13503 hardware functional specification, drawing office number x18a-a-001-xx. 2.2.2 sram access time to support 256 color modes the s1d13503 must be configured to support a 16-bit data path into display memory (sram). for 16-bit display memory interface the required sram access time must be: sram access time < 1/f osc - 40nsec. (3.3v specification) therefore using a 6.0 mhz input clock: sram access time must be < 127 ns. note for a detail description of the sram access time, see section 9.2 of the s1d13503 hardware functional specification, drawing office number x18a-a-001-xx. 3 conclusions to support a 320x240 256 color panel at 70 hz refresh, you require a 6.0 mhz input clock, and 76.8k bytes of 127nsec access time sram. horizontalpixels () verticallines () bitsperpixel () 8 ------------------------------------------------------------------------------------------------------------------------------- --------------
page 8 epson research and development vancouver design center s1d13503 lcd panel options / memory requirements x18a-g-005-05 issue date: 01/01/30 4 implementation 4.1 16-bit display memory interface since 76.8k bytes with at least 127ns access time sram is required, one 64kx16 byte sram with 120ns access time will be used for this example. figure 1: 16-bit memory configuration example 4.1.1 configuration options vd0 = pull-up (with a 10k resistor) for 16-bit bus interface. other option settings are not related to this implementation. s1d13503 vwe# vd0-7 vd8-15 vcs0# vcs1# va 0 - 1 5 sram we# ub# lb# a0-15 i/o 1-8 i/o 9-16 320x240 color lcd ud0-3 ld0-3 yd lp xscl 6.0mhz osc1 64kx16
epson research and development page 9 vancouver design center lcd panel options / memory requirements s1d13503 issue date: 01/01/30 x18a-g-005-05 4.1.2 register settings aux[0] = 0000 0000 not in test mode aux[1] = 1011 100x 8-bit single panel, 256 color, 16-bit display memory interface aux[2] = 1001 1111 horizontal resolution = 320 ; 256 colors = 1 pixels per byte; 1 pixels per fetch aux[3] = 0000 0110 not in power save modes aux[4] = 1110 1111 total 240 scan lines aux[5] = 0000 0000 wf = 0 aux[6] = 0000 0000 aux[7] = 0000 0000 default starting address at 0000h (with aux[6]) aux[8] = xxxx xxxx don ? t care when not using split screen aux[9] = xxxx xxxx don ? t care when not using split screen aux[a] = 1110 1111 together with aux[b] bit1-0, should be the same as or larger than aux[5] bit1-0 and aux[b] = xxxx xx00 aux[4] when not using split screen aux[d] = 0000 0000 no virtual screen x = don ? t care a sample of values for the look up table to produce 256 colors is shown below; red: [00 02 04 06 09 0b 0d 0f]0f 0d 0b 09 06 04 02 00 green:[00 02 04 06 09 0b 0d 0f]0f 0d 0b 09 06 04 02 00 blue: [00 05 0a 0f]0f 0a 05 00 01 06 09 0e 0d 09 04 02 note refer to s1d13503 programming notes and examples, x18a-g-002-xx, for further information.
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s1d13503 dot matrix graphics lcd controller s1d13503 / s1d13502 comparison document number: x18a-g-008-04 copyright ? 1997, 2001 epson research and development, inc. all rights reserved. information in this document is subject to change without notice. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners.
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epson research and development page 3 vancouver design center s1d13503 / s1d13502 comparison issue date: 01/01/30 x18a-g-008-04 1 s1d13503 / s1d13502 comparison the s1d13503 is pin compatible with, and includes all features of the s1d13502. this allows an easy upgrade path for the system designer, both from the hardware and software aspect. the purpose of this document is to briefly describe the differ- ences between these two controllers, for further details refer to the individual hardware functional specifications. 1.1 feature comparison note 16-bit color panel support is provided by the s1d13503 using external logic. all other features not mentioned above are supported by both controllers. see the s1d13503 hardware functional speci- fication, x18a-a-001-xx, and the s1d13502 hardware functional specification, x16-sp-001-xx, for further details. feature s1d13503 s1d13502 color 4 / 16 / 256 colors not available monochrome black-and-white 4 / 16 gray shades not available 4 / 16 gray shades display data formats 4 / 8-bit, single / dual monochrome panel support 4 / 8 / 16-bit single / dual color panel support (note) 4 / 8-bit, single / dual monochrome panel support not available programmable horizontal non-display period yes fixed look-up tables 3x16 position, 4-bit wide look-up tables 1x16 position, 4-bit wide look-up table revision code 2-bit fixed 1-bit fixed
page 4 epson research and development vancouver design center s1d13503 / s1d13502 comparison x18a-g-008-04 issue date: 01/01/30 1.2 s1d13503 register changes / additions from the s1d13502 see the s1d13503 hardware functional specification, x18a-a-001-xx, for details on these registers. aux[01h] bit 2 lcd data width bit 0 bit 3 gray shade / color aux[03h] bit 1 color mode bit 2 bw / 256 colors bit 3 lcd data width bit 1 aux[0ch] bit 0:7 horizontal non-display period aux[0eh] bit 4 id bit / rgb index bit 0 bit 5 id bit / rgb index bit 1 bit 6 green bank bit 0 bit 7 green bank bit 1 aux[0fh] bit 4 blue bank bit 0 bit 5 blue bank bit 1 bit 6 red bank bit 0 bit 7 red bank bit 1

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